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IMX7SCEC Datasheet(PDF) 101 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 101 Page - NXP Semiconductors |
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101 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 101 • For loopback DQS sampling, the data strobe is output to the DQS pad together with the serial clock. The data strobe is looped back from DQS pad and used to sample input data. Figure 73. QuadSPI Output/Write Timing (SDR mode) NOTE Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default value of 3 are shown on the timing. Please refer to the i.MX 6SoloX Reference Manual (IMX6ULLRM) for more details. Table 74. QuadSPI Output/Write Timing (SDR mode) Symbol Parameter Value Unit Min Max TDVO Output data valid time — 2.5 ns TDHO Output data hold time -0.5 — ns TCK SCK clock period 10 — ns TCSS Chip select output setup time 3 — SCK cycle(s) TCSH Chip select output hold time 3 — SCK cycle(s) |
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