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IMX7SCEC Datasheet(PDF) 102 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 102 4.10.10.2 DDR Mode Figure 74. QuadSPI Input/Read Timing (DDR mode with internal sampling) Figure 75. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling) NOTE • For internal sampling, the timing values assumes using sample point 0, that is QuadSPIx_SMPR[SDRSMP] = 0. Table 75. QuadSPI Input/Read Timing (DDR mode with internal sampling) Symbol Parameter Value Unit Min Max TIS Setup time for incoming data 8.67 — ns TIH Hold time requirement for incoming data 0 — ns Table 76. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling) Symbol Parameter Value Unit Min Max TIS Setup time for incoming data 2 — ns TIH Hold time requirement for incoming data 1 — ns |
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