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AD9528 Datasheet(PDF) 41 Page - Analog Devices

Part # AD9528
Description  JESD204B Clock Generator with 14 LVDS/HSTL Outputs
PDF  67 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9528 Datasheet(HTML) 41 Page - Analog Devices

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Data Sheet
AD9528
Rev. D | Page 41 of 67
DEVICE INITIALIZATION AND CALIBRATION FLOWCHARTS
The flowcharts in this section show a typical AD9528
initialization routine using an evaluation software generated
setup file (.stp), and calibration routines designed for robust
system startup.
Figure 52, Figure 53, Figure 54, and Figure 55 assume the
following: dual loop configuration, VCXO with a ±100 ppm
pull range, and a valid frequency translation from a .stp file.
These flowcharts are provided as recommendations.
The count variable for the chip level reset loop (RST_COUNT)
and the count variable for the PLL2 recalibration loop
(CAL_COUNT) are count variables used to establish a count
limit to a loop, such that it is not an infinite loop. These
variables only apply to initialization.



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