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AD9528 Datasheet(PDF) 56 Page - Analog Devices

Part # AD9528
Description  JESD204B Clock Generator with 14 LVDS/HSTL Outputs
PDF  67 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9528 Datasheet(HTML) 56 Page - Analog Devices

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AD9528
Data Sheet
Rev. D | Page 56 of 67
Address
Bits
Bit Name
Description
0x010A
[7:4]
Reserved
Reserved.
3
Holdover mode
High permits the VCXO_CTRL control voltage to be forced to midsupply when the
feedback or input clocks fail. Low tristates the charge pump output.
1 = VCXO_CTRL control voltage goes to VCC/2.
0 = VCXO_CTRL control voltage tracks the tristated (high impedance) charge pump
(through the buffer).
[2:0]
Reference selection mode,
Bits[2:0]
Programs the REFA, REFB mode selection (default = 000).
REF_SEL
Pin
Bit 2
Bit 1
Bit 0
Description
X1
0
0
0
Nonrevertive: stay on REFB.
X1
0
0
1
Revert to REFA.
X1
0
1
0
Select REFA.
X1
0
1
1
Select REFB.
0
1
X1
X1
REF_SEL pin = 0 (low): REFA.
1
1
X1
X1
REF_SEL pin = 1 (high): REFB.
1 X means don’t care.
Table 47. PLL Fast Lock (Register 0x010B)
PLL2 (REGISTER 0x0200 TO REGISTER 0x0209)
Table 48. PLL2 Charge Pump Control (Register 0x0200)
Table 49. PLL2 Feedback VCO CAL Divider Control (Register 0x0201)
Table 50. PLL2 Control (Register 0x0202)
Bits
Bit Name
Description
7
Lock detect power-down enable
Controls power-down of the PLL2 lock detector.
1 = lock detector powered down.
0 = lock detector active.
6
Reserved
Default = 0; value must remain 0.
5
Frequency doubler enable
Enables doubling of the PLL2 reference input frequency.
1 = enabled.
0 = disabled.
Bits
Bit Name
Description
7
PLL1 fast lock enable
Enables PLL1 fast lock operation.
[6:0]
Fast lock charge pump current (μA),
Bits[6:0]
These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA with a
full-scale magnitude of ~63.5 μA.
Bits
Bit Name
Description
[7:0]
PLL2 CP current (μA), Bits[7:0]
These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA with a
full-scale magnitude of ~900 μA.
Bits
Bit Name
Description
[7:6]
A divider, Bits[1:0]
A divider word
[5:0]
B divider, Bits[5:0]
B divider word
Feedback Divider Constraints
A Divider (Bits[7:6])
B Divider (Bits[5:0])
Allowed N Division (4 × B + A)
A = 0 or A = 1
B = 4
N = 16 to 255
A = 0 to A = 2
B = 5
A = 0 to A = 2
B = 6
A = 0 to A = 3
B ≥ 7



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