AD9528 datasheet(55/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 55 of 67

Table 46. PLL1 Input Receiver Control

Address

Bits

Bit Name

Description

0x0108

Frequency detector power-down

enable

1 = enabled.

0 = disabled (default).

REFB differential receiver enable

1 = differential receiver mode.

0 = single-ended receiver mode (also depends on Register 0x0109, Bit 1) (default).

REFA differential receiver enable

1 = differential receiver mode.

0 = single-ended receiver mode (also depends on Register 0x0109, Bit 0) (default).

REFB input receiver enable

REFB receiver power-down control mode.

1 = enable REFB receiver.

0 = power-down (default).

REFA input receiver enable

REFA receiver power-down control mode.

1 = enable REFA receiver.

0 = power-down (default).

VCXO receiver power-down

enable

Enables control over power-down of the VCXO receivers.

1 = power-down control enabled.

0 = both receivers enabled (default).

VCXO single-ended receiver

mode enable CMOS mode

Selects which single-ended input pin is enabled when in the single-ended receiver

mode (Register 0x0108, Bit 0 = 0).

1 = negative receiver from VCXO input (VCXO_IN pin) selected.

0 = positive receiver from VCXO input (VCXO_IN pin) selected (default).

VCXO differential receiver enable

1 = differential receiver mode.

0 = single-ended receiver mode (default).

0x0109

[7:6]

Reserved

Reserved.

N1 feedback divider reset

Puts divider in reset.

1 = Divider held in reset.

0 = divider normal operation.

REFB divider (RB) reset

Puts divider in reset.

1 = Divider held in reset.

0 = divider normal operation.

REFA divider (RA) reset

Puts divider in reset.

1 = Divider held in reset.

0 = divider normal operation.

PLL1 Feedback Divider Source

Selects the input source to the PLL1 feedback divider.

1 = selects VCXO as the input to the PLL1 feedback divider.

0 = selects the PLL2 feedback divider output as the input to the PLL1 feedback

divider.

REFB single-ended negative

pin enable (CMOS mode)

Selects which single-ended input pin is enabled when in single-ended receiver mode

(also depends on Register 0x0108, Bit 6 = 0).

1 = REFB pin enabled.

0 = REFB pin enabled.

REFA single-ended negative pin

mode enable (CMOS mode)

Selects which single-ended input pin is enabled when in single-ended receiver mode

(also depends on Register 0x0108, Bit 5 = 0).

1 = REFA pin enabled.

0 = REFA pin enabled.

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