AD9545BCPZ datasheet(57/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 57 of 157

The user can access the phase slew active results via an

appropriately configured Mx status pin (see the Status and

Control Pins section). The Mx pin output signal constitutes a

logical OR of the DPLLx phase slew active bits on a per channel

basis. That is, the logical OR of the six DPLL0 phase slew active

bits associated with Channel 0 or the logical OR of the four

DPLL1 phase slew active bits associated with Channel 1.

Maximum Phase Slew Step Size

During the execution of a subsequent phase offset, the user

controls the maximum step size of the phase steps via the 3-bit

unsigned maximum phase slew step bit field in Bits[D2:D0] of

0x1123, Register 0x112C, Register 0x1135, Register 0x1508,

Q divider has a dedicated maximum phase slew step bit field

that establishes the maximum phase step size per Table 35 (in

which E is number of Q divider input edges per output period

(see the Initial Phase Offset section) and floor(x) means to

round x to the nearest integer in the direction of −∞). Keep in

mind that Table 35 defines a maximum phase step size during

phase slewing, but the controller may use smaller values to

ensure the terminal phase value does not exceed the value

defined by the Qxy phase bit field.

When maximum phase slew step = 7, the phase controller requires

only one step to reach the desired phase offset regardless of the

size of the phase offset. Therefore, it effectively deactivates the

phase slewing feature. When maximum phase slew step = 7, the

phase controller behaves as though the Qxy phase slew mode

bit is Logic 0 (that is, lag only) even if the Qxy phase slew mode

bit is Logic 1 (see the Phase Slew Mode section).

When maximum phase slew step = 0 or 1, the slewing operation

is limited to half-cycles or full cycles, respectively, of the input

clock. Because this bit setting represents a small maximum

phase step for most Q divider divide ratios, most choices of Qxy

phase incurs phase slewing as though maximum phase slew

step equals 0 or 1.

Table 35. Maximum Phase Slew Step Size

Maximum

Phase Slew

Step Bit Field

Value

Maximum Phase

Step Size (Degrees)

Comment

360 ÷ E

One input half-cycle

180 ÷ E

Two input half-cycles

360 × floor(E/32)/E

~11.25°

360 × floor(E/16)/E

~22.5°

360 × floor(E/8)/E

~45°

360 × floor(E/4)/E

~90°

360 × floor(E/2)/E

~180°

7 (default)

360 × (E − 1)/E

~360°

Maximum phase slew step values greater than 1 require the user

to ensure that the maximum phase step size is greater than or equal

to one input half-cycle. Otherwise, the phase slewing function is

invalid and the device flags an error (via the aforementioned

Channel x phase control error bit). For example, when QN = 5

(that is, E = 10 (see the Initial Phase Offset section)), one half-

cycle constitutes 36°. As such, maximum phase slew step values

of 2 or 3 are invalid and the controller sets the DPLLx phase

control error bit.

Phase Slew Mode

During the execution of a subsequent phase offset, the phase

controller can slew phase in two different modes. The user

selects the mode via the Qxy phase slew mode bits (where x is 0

or 1 and y is A, AA, B, BB, C, or CC) in Bit D3 of Register 0x1108,

0x112C, Register 0x1135, Register 0x1508, Register 0x1511,

When Qxy phase slew mode is Logic 0 (default), the phase

controller slews phase in the direction that reduces the output

frequency during the stepwise phase adjustment sequence.

Alternatively, when Qxy phase slew mode is Logic 1, the phase

controller slews phase in the direction requiring the fewest

number of steps. An exception is when enable Qxy half divide =

1 and the desired phase shift is within one Q divider input half-

cycle of the midpoint of an output cycle. In this case, the phase

controller may choose the slightly longer direction. When Qxy

phase slew mode = 1, the output frequency may change in

either direction, as required, for any given stepwise phase

adjustment sequence (due to the phase controller choosing the

direction of the fewest number of steps).

Output Pulse Width Control

By default, the Q divider output generates a clock signal with a

50% pulse width. However, the user has the option to control

the pulse width of the Q divider output. The control granularity

is one half-cycle of the input clock of the Q divider. Pulse width

control is via the enable Qxy pulse width control bit (where x is 0 or

1 and y is A, AA, B, BB, C, or CC) in Bit D4 of Register 0x1108,

0x1111, Register 0x111A, Register 0x1123, Register 0x112C,

0x151A, and Register 0x1523.

To set the pulse width, program the desired pulse width via the

Qxy phase bit field and set the corresponding enable Qxy pulse

width control bit to Logic 1. Then, assert the IO_UPDATE bit.

When enable Qxy pulse width control = 1, the phase controller

interprets the Qxy phase bit field as a pulse width value rather

than a phase offset value.

The Qxy phase bit field relates to the pulse width as follows:

Pulse width (%) = 100 × Qxy phase/E

(2)

where:

Pulse width defines the portion of an output clock cycle from

the rising edge to the falling edge.

E is as defined in the Initial Phase Offset section.

AD9545BCPZ Datasheet(PDF) 57 Page - Analog Devices

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