AD9545BCPZ datasheet(92/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 92 of 157

To specify a hold off period, program the 8-bit unsigned DPLLx

history hold off time bit field (where x is 0 or 1) in Register 0x1010

and Register 0x1410 with a non-zero value. The hold off period

relates to the bit field value as follows:

Hold off period = DPLLx history hold off time × (tHAT

/8)

where tHAT is the time specified by the DPLLx history accumulation

timer bit field (where x is 0 or 1). See the Averaging Processor

Windowed Average section for details on the DPLLx history

accumulation timer bit field.

The timed delay (if enabled) is also in effect following a

pause/restart trigger event (see the Averaging Processor

Continue or Reset section).

Averaging Processor Windowed Average

The DPLLX History Accumulation Timer Bit Field

In general, the averaging processor collects tuning word

samples generated by the loop filter and computes an average of

the tuning word samples. The user specifies an averaging

window for the rolling average time span via the 28-bit

unsigned DPLLx history accumulation timer bit field (where x

is 0 or 1). The DPLLx history accumulation timer bit field resides

in Register 0x100A to Register 0x100D and Register 0x140A to

The units associated with the DPLLx history accumulation

timer bit field are milliseconds. The 28-bit range of the DPLLx

history accumulation timer bit field allows averaging time spans

from 0.001 sec to 268,435.455 sec (~74.5 hours). The default

value (0x0000000A) of the DPLLx history accumulation timer

provides an averaging window time span of 10 ms.

The averaging window time span relates to the value of the

DPLLx history accumulation timer bit field as follows:

Time span = DPLLx history accumulation timer × 10−3

The recommended minimum averaging window time span is at

least 10 times the minimum expected period of the signal at the

input to the phase/frequency detector of the DPLL.

Determine the value of the DPLLx history accumulation timer

bit field necessary to provide a 15-minute windowed average.

Solving the time span equation for the bit field value yields:

DPLLx History Accumulation = Time span × 1000

= (15 × 60) × 1000

= 900,000

= 0x00DBBA0 (hexadecimal)

Programming DPLLx history accumulation timer = 0 is a

special case; it bypasses the averaging processor by routing

tuning word samples from the digital loop filter to both the

DPLL NCO and the 46-bit tuning word history bit field. Thus,

programming DPLLx history accumulation timer = 0 makes it

possible to monitor tuning words directly from the loop filter as

they are applied to the DPLL NCO. The DPLLx history available

status bit (Bit D0 of Register 0x3102 and Register 0x3202) is Logic 0

when DPLLx history accumulation timer = 0.

Changing the value of the DPLLx history accumulation timer

bit field exhibits different behavior depending on the current

state of the history circuit. The value matters only during hold

off and active operation, in which case the history processor

uses the new value (though there may be a delay associated

with the old value before the update takes effect). The circuit

does not change states when the value of the DPLLx history

accumulation timer bit field is changed.

Updating the timer value while actively collecting history causes

future intervals to conform to the new value. If the elapsed

period of the current interval exceeds that of the new interval,

the next interval begins immediately. Otherwise, the current

interval conforms to the new value.

However, if the history circuit is in the hold-off state (see the

Averaging Processor Delay section), behavior is slightly

different. The number of 1/8th intervals already completed

remains unchanged regardless of the actual time elapsed. Future

1/8th intervals uses the new period. However, the current 1/8th

interval continues to use the old value.

Note that changing the DPLLx history hold off time bit field

value (see the Averaging Processor Delay section) has no effect

until the beginning of the next hold-off period (in its entirety,

not a sub-interval). If the behavior associated with the hold-off

period, due to updating either the history period or the hold-off

value, needs to reflect the new value as soon as possible, the

user can restore the history circuit to its initialization state via

the DPLLx clear history bit (see the DPLLx Clear History Bit

section).

Tuning Word Averaging Process

In operation, the averaging processor performs averaging by

partitioning the time span defined by the DPLLx history

accumulation timer bit field into eight subintervals. During

each sub-interval, the averaging processor computes the average

of the tuning word samples for that subinterval. A full tuning

word average, as defined by the DPLLx history accumulation

timer bit field, constitutes the average of eight consecutive sub-

interval averages.

At the termination of each successive sub-interval (given the

averaging processor has set the DPLLx history available bit) the

averaging processor triggers the following events:

•

Update the rolling average computation

•

Save the result to the DPLLx tuning word history bit field

•

Update the IRQ circuitry via the DPLLx history update bit

As such, at the end of each subinterval, the averaging processor

stores the result of the updated rolling average computation in

the DPLLx tuning word history bit field. At the same time, the

averaging processor sets the DPLLx history updated bit to Logic 1.

The DPLLx history updated bit provides the user with a

mechanism for knowing when the DPLLx tuning word history

AD9545BCPZ Datasheet(PDF) 92 Page - Analog Devices

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