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AD9545BCPZ Datasheet(PDF) 59 Page - Analog Devices |
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AD9545BCPZ Datasheet(HTML) 59 Page - Analog Devices |
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59 / 157 page  Data Sheet AD9545 Rev. A | Page 59 of 157 DISTRIBUTION N-SHOT/PRBS OUTPUT CLOCKING N-SHOT/PRBS CLOCKING OVERVIEW The Q dividers work in conjunction with several controllers, one of which is the N-shot/pseudorandom binary sequence (PRBS) controller (see Figure 47). The N-shot/PRBS controller provides the AD9545 with the capability of generating system reference (SYSREF) and device clock (DEVCLK) clocks per the JESD204B standard as well as gapped and pseudorandom clock signals. A block diagram of the N-shot/PRBS clock controller appears in Figure 48, which includes a more detailed representation of the relationship between the Q dividers, the modulation controller and the N-shot/PRBS controller. In the text that follows, Qxy denotes a particular Q divider, whereas Qxy denotes its output (where x is 0 and y is A, AA, B, BB, C, or CC). For example, Q0A is the output of Q divider, Q0A. Although Figure 48 is specific to PLL Channel 0, it is also representative of PLL Channel 1, because there are dedicated controllers for each PLL channel. Note that the Q0AA, Q0BB, and Q0CC outputs route directly to the N-shot/PRBS controller, whereas Q0A, Q0B, and Q0C route through the modulation controller. As such, the Q0A, Q0B, and Q0C outputs are the only ones subject to modulation (see the Distribution Embedded Output Clock Modulation section). However, disabled (default) modulation channels have an internal bypass allowing the Q0A, Q0B, and Q0C outputs to pass directly through the modulation controller. AA Q0A Q0AA FROM SYSTEM CLOCK FROM PLL0 Q-DIVIDER PAIR N-SHOT/PRBS CONTROLLER TRIGGER N GAP OUT PRBS GENERATOR A N-SHOT N-SHOT GAP N-SHOT/PRBS GENERATOR A N-SHOT REQUEST CHANNEL X ENABLE N-SHOT RETIME ENABLE SYSCLK Q0A TO OUTPUT DRIVERS N-SHOT GENERATOR A MODE N-SHOT REQUEST MODE 0 1 Q-DIVIDER PAIR Q0B Q0BB Q-DIVIDER PAIR Q0C Q0CC INA OUT0AP INB INC MODULATION CONTROLLER SIGA SIGAA SIGB SIGBB SIGC SIGCC TRIGGER MODE SIGA INTERNAL/EXTERNAL ZERO DELAY FEEDBACK PATH FDBK CLOCK TO DPLL0 N-DIVIDER PROFILE x.y TAG MODE 5 SIGA SIGB SIGC SIGAA SIGCC SIGBB SYNC SIGA SIGB SIGC TEXT = BIT(S) IN THE REGISTER MAP N-SHOT RETIME N-SHOT RETIMING MUX N-SHOT REQUEST OUT0AN HITLESS/ZERO DELAY FEEDBACK AND SYNC 3 SIGB SIGAA B SIGC SIGBB SIGCC TRIGGER MODE GAP N SNCA SNCB SNCC SNCA SNCB SNCC TRIGGER MODE SIGA SIGB SIGC SIGAA SIGCC SIGBB SNCA SNCB SNCC CC BB C OUT0BP OUT0BN OUT0CP OUT0CN Figure 48. Block Diagram of JESD204B/Gapped Clock Controller |
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