LTC6952 datasheet(41/80 Pages) AD

41 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

EZS_SRQ INPUT

The LTC6952’s EZS_SRQ input buffer, shown in Figure 9,

controls synchronization requests and SYSREF requests.

All connections must be DC-coupled and can be either

differential CML or LVPECL, differential LVDS with a level-

shifting network, or single-ended 1.8V to 3.3V CMOS into

the EZS_SRQ+ input pin (EZS_SRQ– must be grounded

for CMOS drive). Figure 27 shows the recommended

interface types.

JESD204B DESIGN EXAMPLE USING EZSync

STANDALONE

This design example consists of a system of two JESD204B

analog-to-digital converters (ADCs), two JESD204B digital-

to-analog converters (DACs), and a JESD204B compatible

FPGA. All of the data converters (ADCs and DACs) and

the FPGA require JESD204B subclass 1 device clocks and

SYSREFs, and the FPGA requires an extra management

750Ω

50Ω

100Ω

130Ω

100Ω

150Ω

DC-COUPLED DIFFERENTIAL LVDS

LTC6952

LVDS

6952 F27

LTC6952

CML

DC-COUPLED DIFFERENTIAL CML*

LTC6952

1.8V to 3.3V

CMOS

1.8V to 3.3V CMOS

3.3V

LTC6952

LVPECL

DC-COUPLED DIFFERENTIAL LVPECL*

* Output common mode levels of differential drivers must be

within the min and max EZS_SRQ input common mode levels

speciﬁed in the Electrical Characteristics.

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

–

Figure 27. Common EZS_SRQ Input Interface Configurations. All Z0 Signal Traces are 50Ω Transmisson Lines

clock. Additionally, the ADCs require a low noise clock of

less than 100fs total RMS jitter. This leads to a total of 11

separate signals to generate, with frequencies listed below.

For this example, the SYSREF frequencies for all devices

are the same and should output four pulses upon a SYSREF

request rising edge:

fADC-CLK = 500MHz

fDAC-CLK = 4000MHz

fFPGA-CLK = 125MHz

fFPGA-MGMT = 100MHz

fSYSREF = 12.5MHz

Since the total number of outputs is 11, a single LTC6952

can be used to generate all of the outputs needed as

shown in Figure 28. Note that termination resistors and

AC coupling caps are not shown for clarity.

LTC6952 Datasheet(PDF) 41 Page - Analog Devices

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