LTC6952 datasheet(65/80 Pages) AD

65 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

IN-BAND OUTPUT PHASE NOISE

The in-band phase noise floor LOUT produced at fOUTx may

be calculated by using Equation 20.

LOUT = LNORM + 10 • log10(fPFD)

+ 20 · log10(fOUTx/fPFD)

LOUT = LNORM + 10 • log10(fPFD)

+ 20 • log10(N/Mx)

(20)

where LNORM is –229dBc/Hz.

As can be seen, for a given PFD frequency fPFD, the output

in-band phase noise increases at a 20 dB-per-decade rate

with the N divider count. So, for a given output frequency

fOUTx, fPFD should be as large as possible (or N should be

as small as possible) while still satisfying the application’s

frequency step size requirements.

OUTPUT PHASE NOISE DUE TO 1/f NOISE

In-band phase noise at very low offset frequencies may

be influenced by the LTC6952’s 1/f noise, depending upon

fPFD. Use the normalized in-band 1/f noise L1/f of –277dBc/

Hz with Equation 21 to approximate the output 1/f phase

noise at a given frequency offset fOFFSET:

LOUT(1/f) (fOFFSET) = L1/f + 20 • log10(fOUTx)

- 10 • log10(fOFFSET)

(21)

Unlike the in-band noise floor LOUT, the 1/f noise LOUT(1/f)

does not change with fPFD, and is not constant over offset

frequency. See Figure 38 for an example of in-band phase

noise for fPFD equal to 5MHz and 100MHz. The total phase

noise will be the summation of LOUT and LOUT(1/f).

REFERENCE SIGNAL ROUTING, SPURIOUS, AND

PHASE NOISE

The charge pump operates at the PFD’s comparison

frequency fPFD. The resultant output spurious energy is

small and is further reduced by the loop filter before it

modulates the VCO frequency.

APPLICATIONS INFORMATION

TOTAL NOISE

fPFD = 5MHz

TOTAL NOISE

fPFD = 100MHz

1/f NOISE

CONTRIBUTION

OFFSET FREQUENCY (Hz)

100

10k

100k

–125

–120

–115

–110

–105

–100

–95

–90

6952 F38

Figure 38. Theoretical In-Band Phase Noise, fOUTx = 4500MHz

However, improper PCB layout can degrade the LTC6952’s

inherent spurious performance. Care must be taken to

prevent the reference signal fREF from coupling onto the

VCO’s tune line, or into other loop filter signals. Example

suggestions are the following.

1. Do not share power supply decoupling capacitors

between same-voltage power supply pins.

2. Use separate ground vias for each power supply

decoupling capacitor, especially those connected to

VREF+, VD+, VOUT+, VCP+, and VVCO+.

3. Physically separate the reference frequency signal

from the loop filter and VCO.

REFERENCE SIGNAL AND EZS_SRQ TIMING FOR

ParallelSync MODE

Setting PARSYNC to “1” requires tighter timing between

the REF± inputs and the EZS_SRQ input. The LTC6952

is designed to allow sine wave or square wave reference

inputs at various levels and all settings of BST or FILT, and

have consistent performance with respect to setup and

hold times of the EZS_SRQ input pulse. The parameters

tSS and tSH are tested and specified for both CMOS and

differential input levels applied to REF± and EZS_SRQ±,

having the performance characteristics shown in Figure 39

for EZS_SRQ± rising and Figure 40 for EZS_SRQ± falling.

For CMOS EZS_SRQ signals, VIH = 1.3V and VIL = 0.6V.

For differential EZS_SRQ signals, VIH = VIL = 50% of the

signal swing. The trip point for any type of REF± input is

always 50%.

LTC6952 Datasheet(PDF) 65 Page - Analog Devices

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