LTC6952 datasheet(60/80 Pages) AD

60 / 80 page

LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Determining Output Digital Delay Values

In order to calculate each parallel LTC6952 output’s delay

value for this design example, use the following procedure:

1. Delay all of the JESD204B device clocks by half of a

period of the slowest JESD204B device clock. This

delay setting is equal to the divide value of the slowest

device clock because a one code digital delay equals

half of a VCO cycle. Non-JESD204B clocks (such as

the FPGA management clock) are not included in

this calculation. This delay value defines the desired

SYSREF valid clock edge. In this example, the slowest

JESD204B clock is the FPGA device clock:

DDELSYSvalid = MFPGACLK = 20

DDELADC-CLK´ = DDELSYSvalid = 20

DDELFPGA-CLK´ = DDELSYSvalid = 20

2. For each device clock/SYSREF pair, subtract half a

device clock period from DDEL to find the SYSREF

delay. This is equivalent to subtracting the correspond-

ing divide value of the device clock, i.e.

DDELADC-SYS´ = DDELSYSvalid – MADC-CLK

DDELADC-SYS´ = 20 – 10 = 10

DDELFPGA-SYS´ = DDELSYSvalid – MFPGA-CLK

DDELFPGA-SYS´ = 20 – 20 = 0

3. Although not usually required, the outputs can be

aligned to the incoming reference. To achieve this, ad-

ditional digital delay is added to each parallel LTC6952

output to align it with the next reference edge. This

delay can be calculated by Equation 18:

DDELREF-OS = 2 • N • CEILING(16/(2•N)) – 16

(18)

where CEILING() means round up to the nearest integer.

Remembering that the N value was previously calculated

to be 24, the result of this equation is 32. Add 32 to all of

the parallel LTC6952s DDEL values if reference alignment

is desired. For this example, reference alignment is not

necessary.

Even though OUT1 and OUT3 on the reference LTC6953

are only passing through the SYNC/SRQ pulse, their digital

delays should be set so that its edges occur on the falling

edge of their corresponding reference clocks. This is to

ensure that the EZS_SRQ signals into the parallel ICs have

a proper setup and hold time relationship to the reference

clock. Since the reference LTC6953 has its reference clock

output dividers set to 2 and DDEL set to 0, the passthrough

output DDELs should be set to 2 based on Table 18.

All of the calculated digital delay values are shown in

Table 32.

Table 32. Output DDELx Settings for ParallelSync Example

OUTPUT

PURPOSE

DDELx

OUT0

LTC6952 #1 REF

OUT1

LTC6952 #1 EZS-SRQ

OUT2

LTC6952 #2 REF

OUT3

LTC6952 #2 EZS-SRQ

OUT4-10

Unused

N/A

OUT0

Unused

N/A

OUT1

ADC0 SYSREF

OUT2

ADC0 CLK

OUT3

ADC1 SYSREF

OUT4

ADC1 CLK

OUT5

ADC2 SYSREF

OUT6

ADC2 CLK

OUT7

ADC3 SYSREF

OUT8

ADC3 CLK

OUT9

Unused

N/A

OUT10

FPGA MGMT CLK

OUT0

Unused

N/A

OUT1

FPGA SYSREF

OUT2

FPGA DEV CLK

OUT3

ADC4 SYSREF

OUT4

ADC4 CLK

OUT5

ADC5 SYSREF

OUT6

ADC5 CLK

OUT7

ADC6 SYSREF

OUT8

ADC6 CLK

OUT9

ADC7 SYSREF

OUT10

ADC7 CLK

Now that the output divider and delays have been deter-

mined, the ICs can be programmed.

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