LTC6952 datasheet(70/80 Pages) AD

70 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

terminating impedance results in a portion of the signal

reflecting back toward the other end of the transmission

line. In the extreme case of an open or short circuit termina-

tion, all of the signal is reflected back. This signal reflection

leads to overshoot and ringing on the waveform. Figure 46

shows the preferred method of far-end termination of the

transmission line.

6952 F46

100Ω

Figure 46. Far-End Transmission Line Termination (Z0 = 50Ω)

USING THE LTC6952 TO DRIVE DEVICE CLOCK

INPUTS

The LTC6952’s CML outputs are designed to interface with

standard CML or LVPECL devices while driving transmis-

sion lines with far-end termination. Figure 47 shows DC

coupled and AC coupled output configurations for the CML

outputs. Note that some receiver devices have the 100Ω

termination resistor internal to the part, in which case the

external 100Ω resistor is unnecessary.

6952 F47

LTC6952

100Ω

ADC, DAC,

OR FPGA

ADC, DAC,

OR FPGA

OUTx+

OUTx–

100Ω

OUTx+

OUTx–

CLK+

CLK–

CLK+

CLK–

DEVICES THAT

CAN ACCEPT A

2.3V COMMON

MODE SIGNAL

AC-COUPLED INTO

LVDS OR DEVICES

REQUIRING A SELF-

BIASED INPUT

Figure 47. OUTx CML Connections to

Device Clock Inputs (Z0 = 50Ω)

USING THE LTC6952 TO DRIVE DC COUPLED SYSREF

INPUTS

For JESD204B applications, the SYSREF signal would

ideally be DC coupled from the LTC6952 to the data con-

verter or FPGA as shown in Figure 48. This is possible for

receiver devices that can accept a 2.3V common mode

input signal. Note that some receiver devices have the

100Ω termination resistor internal to the part, in which

case the external 100Ω resistor is unnecessary.

100Ω

OUTx+

OUTx–

6952 F48

LTC6952

ADC,DAC,

or FPGA

DEVICES THAT CAN

ACCEPT A 2.3V

COMMON MODE

SIGNAL

SYSREF+

SYSREF–

Figure 48. OUTx CML DC Coupled Connections to SYSREF Inputs

Use the following procedure to achieve correct JESD204B

SYSREF behavior for DC coupled SYSREFs in any mode.

These methods assume that the SYSREF outputs have

already been synchronized and that the SYSREF output

drivers have been disabled for power savings (PDx = 2).

DC Coupled SYSREFs (MODEx = 0, 1, or 3)

1. Enable the LTC6952 SYSREF output drivers by setting

PDx = 0 and set SRQMD = 1.

2. Set the receiver device to accept SYSREFs.

3. Set SSRQ or the EZS_SRQ inputs to “1” for at least

1ms, then set back to “0”.

4. After the SYSREFs have been accepted by the receiver

device, set the device to stop accepting SYSREFs.

5. Disable the LTC6952 SYSREF output drivers by setting

PDx = 2 and set SRQMD = 0.

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