LTC6952 datasheet(27/80 Pages) AD

27 / 80 page

LTC6952

6952f

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

160Ω

100Ω

160Ω

100Ω

160Ω

100Ω

160Ω

100Ω

160Ω

100Ω

OUTx±

EZS_SRQ+

VCO+

REF±

OUT0+

OUT1+

EZS_SRQ+

EZS_SRQ–

OUT10+

OUT2+

OUT3+

OUT4+

OUT5+

OUT6+

OUT7+

OUT8+

OUT9+

LTC6953 or LTC6952

11 OUTPUTS

LF(s)

VCO±

VCO

REF

LTC6952

EZSYNC

CONTROLLER

OUT0–

VCO–

LTC6953 or LTC6952

OUT1–

OUTx±

VCO+

LTC6953 or LTC6952

11 OUTPUTS

VCO–

LTC6953 or LTC6952

OUT2–

OUT3–

OUTx±

VCO+

11 OUTPUTS

VCO–

OUTx±

VCO+

11 OUTPUTS

VCO–

OUT4–

OUT5–

OUT6–

OUT7–

OUTx±

VCO+

11 OUTPUTS

VCO–

LTC6953 or LTC6952

OUT10–

OUT8–

OUT9–

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

EZS_SRQ+

EZS_SRQ–

FOLLOWER-SYNCHRONOUS OUTPUT

ALL CONTROLLER TO FOLLOWER

CONNECTIONS MUST BE DC COUPLED

CONTROLLER

FOLLOWERS

6952 F12

SYNC OR

SYSREF

REQUEST:

TOGGLE PIN

OR WRITE

SSRQ BIT

REF±

OUTx±

EZS_SRQ±

LF(s)

VCO±

LTC6952

REF±

OUTx±

EZS_SRQ±

LF(s)

VCO±

LTC6952

REF±

OUTx±

EZS_SRQ±

VCO±

LTC6952

REF±

OUTx±

EZS_SRQ±

VCO±

LTC6952

LF(s)

11 OUTPUTS

VCO

REFERENCE

DISTRIBUTION

EZS_SRQ

DISTRIBUTION

REFERENCE MAY BE

SINGLE-ENDED OR DIFFERENTIAL

EZS_SRQ MAY BE

SINGLE-ENDED OR DIFFERENTIAL

6952 F13

Figure 12. EZSync Multi-Chip Synchronization

with Request Passthrough

Figure 13. ParallelSync Multi-Chip Synchronization

For all cases of EZSync synchronization, the CONTROL-

LER must be programmed to output seven pre-pulses to

each FOLLOWER before the FOLLOWER outputs or any

follower-synchronous CONTROLLER outputs start clock-

ing. Additionally, a CONTROLLER must have bit EZMD set

to “0” and a FOLLOWER must have both EZMD and PDPLL

set to “1”. See the Applications Information section for a

programming example. Additionally, the LTC6952Wizard

provides programming guidance.

ParallelSync

In a ParallelSync application, multiple ParallelSync compat-

ible devices are connected in parallel with a shared distrib-

uted REF signal as shown in Figure 13. The advantage of

parallel connection is improved jitter performance, as the

clock signals do not propagate through two or more cas-

caded devices. However, synchronization requires tighter

control of the SYNC and SYSREF request (SRQ) signals’

timing because of the need to have the SYNC/SRQ edges

fall within the same REF cycle for all connected devices.

See Reference Signal and EZS_SRQ Timing for PARSYNC

Mode in the Applications Information section for the timing

requirements of EZS_SRQ to REF in this mode.

LTC6952 Datasheet(PDF) 27 Page - Analog Devices

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