MSM66577 datasheet(17/34 Pages) OKI

17 / 34 page

PEDL66577-01

1Semiconductor

MSM66577 Family

17/34

External data memory control

DD = 4.5 to 5.5 V, Ta = –30 to +70°C)

Parameter

Symbol

Condition

Min.

Max.

Unit

Cycle time

cyc

OSC = 30 MHz

33.3

—

Clock pulse width (HIGH level)

tφWH

—

Clock pulse width (LOW level)

tφWL

—

ALE pulse width

2 t

φ – 10

—

RD pulse width

2 t

φ – 15

—

WR pulse width

2 t

φ – 15

—

RD pulse delay time

RAD

φ – 3

—

WR pulse delay time

WAD

φ – 3

—

Low address setup time

ALS

2 t

φ – 15

—

Low address hold time

ALH

φ – 3

—

High address setup time

AHS

3 t

φ – 25

—

High address hold time

AHH

φ – 3

—

Read data setup time

—

Read data hold time

φ – 3

Write data setup time

φ – 30

—

Write data hold time

L = 50 pF

φ – 3

—

Note: t

φ = t

cyc/2

DIN0 to 7

RAP8 to 19

cyc

tφ

CPUCLK

A8 to A19

AD0 to AD7

ALE

RAP0 to 7

DOUT0 to 7

A8 to A19

AD0 to AD7

RAP0 to 7

Bus timing during no wait cycle time

RAP8 to 19

tφ

RAD

ALS

ALH

AHH

AHS

WAD

ALS

ALH

AHH

AHS

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