SYNPWM datasheet(32/57 Pages) FEELING

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FM8P73B

Web site: http://www.feeling-tech.com.tw

Rev1.0 Nov 20, 2013

P.32/FM8P73B

FEELING

TECHNOLOGY

Example 2.7: External IOB0 pin change wakeup interrupt

Address

Code

#include

<8P73B.ASH>

…

MOVIA

0xFF

n+1

MOVAR

IOSTB

;Set Port B as input

n+2

MOVIA

0xA0

n+3

MOVAR

INTEN

;Enable global & Port B interrupt

n+4

MOVIA

0xDF

n+5

MOVAR

INTFALG

;Clear PBIF flag(Note1)

n+6

MOVR

PORTB,R

;Update Port B pin status

n+7

MOVIA

0x01

n+8

MOVAR

INTPB

;Set IOB0 pin change wakeup

n+9

SLEEP

n+10

NOP

…

N/A

ISR:

;In this example, ISR define at 0x200

200

…

;User Port B pin change wakeup ISR code

200+n

MOVIA

0xDF

200+n+1

MOVAR

INTFLAG

;Clear PBIF flag(Note1)

200+n+2

RETFIE

3FE

GOTO

ISR

3FF

GOTO

START

Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).

2. Interrupt save status code is not shown in this example.

2.7.2

Timer1~3 Interrupt Function

2.7.2.1

Timer1 (PWM1) interrupt

At Timer mode, an underflow (00h  FFh) in the TMR1 counter will set the flag bit T1P1IF (INTFLAG<0>). This

interrupt can be disabled by clearing T1P1IE bit (INTEN<0>).

At PWM mode, the end of each PWM period cycle to generate an interrupt. The interrupt rate can be adjusted by

PIR13:10 (PWM1CON <3:0>).

Figure 2.9: PWM Interrupt Waveform (Normal PWM or Sync PWM mode)

PWM1 Output

T1P1IF (PIR1<3:0>=1:4)

T1P1IF (PIR1<3:0>=1:5)

2.7.2.2

Timer2 interrupt

At Timer mode, an underflow (00h  FFh) in the TMR2 counter will set the flag bit T2IF (INTFLAG<1>). This

interrupt can be disabled by clearing T2IE bit (INTEN<1>).

At PWM mode, TMR2 is PWM1 duty cycle counter. Not generate an interrupt.

2.7.2.3

Timer3 interrupt

An underflow (00h  FFh) in the TMR3 counter will set the flag bit T3IF (INTFLAG<2>). This interrupt can be

disabled by clearing T3IE bit (INTEN<2>).

1. IOB0 pin change

2. Return from ISR

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