SYNPWM datasheet(28/57 Pages) FEELING

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FM8P73B

Web site: http://www.feeling-tech.com.tw

Rev1.0 Nov 20, 2013

P.28/FM8P73B

FEELING

TECHNOLOGY

Example 2.5: Typical Watchdog Reset

Address

Code

#include

<8P73B.ASH>

…

CLRWDT

n+1

MOVIA

0x07

n+2

MOVAR

WDTCON

;Sleep: 2.56S + Wakeup:20mS

n+3

…

n+4

…

n+5

SLEEP

n+6

NOP

…

0x3FF

GOTO

START

2.6

Reset

FM8P73B device may be RESET in one of the following ways:

Power-on Reset (POR)

Brown-out Reset (BOR)

RSTB Pin Reset

WDT time-out Reset

Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and

unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or

WDT Reset.

A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely

ties the RSTB pin to Vdd.

On-chip Low Voltage Detector (LVDT) places the device into reset when Vdd is below a fixed voltage. This

ensures that the device does not continue program execution outside the valid operation Vdd range. Brown-out

RESET is typically used in AC line or heavy loads switched applications.

A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before

SLEEP.

The TO

̅̅̅̅ and PD

̅̅̅̅ bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.

2.6.1

Power-up Reset Timer(PWRT)

The Power-up Reset Timer provides a nominal 20ms delay after Power-on Reset (POR), Brown-out Reset (BOR),

RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.

The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.

Figure 2.7: Reset Timing

Note: TPWRT = 20mS

Case1: LVDT ON, RSTB Disable

Internal Reset

PWRT time-out

TPWRT

VDD

VLVDT

WDT Reset

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