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NT5CC128M8GP-EKB Datasheet(PDF) 139 Page - Nanya Technology Corporation.

Part # NT5CC128M8GP-EKB
Description  Commercial, Industrial and AutomotiveDDR3(L) 1 Gb SDRAM
PDF  160 Pages
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Manufacturer  NANYA [Nanya Technology Corporation.]
Direct Link  http://www.nanya.com
Logo NANYA - Nanya Technology Corporation.

NT5CC128M8GP-EKB Datasheet(HTML) 139 Page - Nanya Technology Corporation.

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Version 2.2
139
Nanya Technology Cooperation ©
04/2019
All Rights Reserved.
NTC Proprietary
Level: Property
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8GN / NT5CB(C)64M16GP
AC & DC Operating Conditions
Timing Parameters (Data rate 1333,1066 and 800 specificatoins and conditions)
Parameter
Symbol
DDR3-800
DDR3(L)-1066
DDR3(L)-1333
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK (DLL_off)
8
-
8
-
8
-
ns
Average Clock Period
tCK(avg)
Refer to “FundamentalAC Specifications”
ps
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT (per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Clock Period Jitter
JIT(per)
-100
100
-90
90
-80
80
ps
Clock Period Jitter during DLL locking period
JIT(per, lck)
-90
90
-80
80
-70
70
ps
Cycle to Cycle Period Jitter
tJIT(cc)
200
180
160
ps
Cycle to Cycle Period Jitter during DLL
locking period
JIT(cc, lck)
180
160
140
ps
Duty Cycle Jitter
tJIT(duty)
-
-
-
-
-
-
ps
Cumulative error across n = 2, 14 . . . 49, 50
cycles
tERR(nper)
tERR(nper) min = (1 + 0.68ln(n)) * tJIT(per)min
tERR (nper) max = (1 + 0.68ln(n)) * tJIT (per)max
ps
Data Timing
DQS,
 to DQ skew, per group, per
access
tDQSQ
-
200
-
150
-
125
ps
DQ output hold time from DQS,

tQH
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK,

tLZ(DQ)
-800
400
-600
300
-500
250
ps
DQ high impedance time from CK,

tHZ(DQ)
-
400
-
300
-
250
ps
Data setup time to DQS,
 referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
DDR3-AC175
75
-
25
-
-
-
ps
tDS(base)
DDR3-AC150
125
-
75
-
30
-
ps
tDS(base)
DDR3L-AC160
90
-
40
-
-
-
ps
tDS(base)
DDR3L-AC135
140
-
90
-
45
-
ps
Data hold time from DQS,
 referenced
to
Vih(dc) / Vil(dc) levels
tDH(base)
DDR3-DC100
150
-
100
-
65
-
ps
tDH(base)
DDR3L-DC90
160
-
110
-
75
-
ps
DQ and DM Input pulse width for each input
tDIPW
600
-
490
-
400
-
ps
Data Strobe Timing
DQS,
 differential READ Preamble
tRPRE
0.9
Note 19
0.9
Note 19
0.9
Note 19
tCK(avg)
DQS,
 differential READ Postamble
tRPST
0.3
Note 11
0.3
Note 11
0.3
Note 11
tCK(avg)
DQS,
 differential output high time
tQSH
0.38
-
0.38
-
0.4
-
tCK(avg)
DQS,
 differential output low time
tQSL
0.38
-
0.38
-
0.4
-
tCK(avg)
DQS,
 differential WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK(avg)
DQS,
 differential WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK(avg)
DQS,
 rising edge output access time
from rising CK,

tDQSCK
-400
400
-300
300
-255
255
ps
DQS and
 low-impedance time
(Referenced from RL
– 1)
tLZ(DQS)
-800
400
-600
300
-500
250
ps
DQS and
 high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
400
-
300
-
250
ps
DQS,
 differential input low pulse width tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK(avg)
DQS,
 differential input high pulse width tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK(avg)
DQS,
 rising edge to CK,  rising edge tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK(avg)
DQS,
 falling edge setup time to
CK,
 rising edge
tDSS
0.2
-
0.2
-
0.2
-
tCK(avg)
DQS,
 falling edge hold time from
CK,
 rising edge
tDSH
0.2
-
0.2
-
0.2
-
tCK(avg)



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