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NT5CC128M8GP-EKB Datasheet(PDF) 142 Page - Nanya Technology Corporation. |
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NT5CC128M8GP-EKB Datasheet(HTML) 142 Page - Nanya Technology Corporation. |
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142 / 160 page  Version 2.2 142 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Timing Parameters (Data rate 2133,1866,1600 specifications and conditions) Parameter Symbol DDR3(L)-1600 DDR3(L)-1866 DDR3-2133 Unit Min. Max. Min. Max. Min. Max. Clock Timing Minimum Clock Cycle Time (DLL off mode) tCK (DLL_off) 8 - 8 - 8 - ns Average Clock Period tCK(avg) Refer to “FundamentalAC Specifications” Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg) Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg) Absolute Clock Period tCK(abs) Min.: tCK(avg)min + tJIT(per)min Max.: tCK(avg)max + tJIT(per)max Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg) Absolute clock LOW pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg) Clock Period Jitter JIT(per) -70 70 -60 60 -50 50 ps Clock Period Jitter during DLL locking period JIT(per, lck) -60 60 -50 50 -40 40 ps Cycle to Cycle Period Jitter tJIT(cc) 140 120 100 Cycle to Cycle Period Jitter during DLL locking period JIT(cc, lck) 120 100 80 Duty Cycle Jitter tJIT(duty) - - - - - - ps Cumulative error across n = 2, 14 . . . 49, 50 cycles tERR(nper) tERR(nper) min = (1 + 0.68ln(n)) * tJIT(per)min tERR (nper) max = (1 + 0.68ln(n)) * tJIT (per)max ps Data Timing DQS, to DQ skew, per group, per access tDQSQ - 100 - 85 - 75 ps DQ output hold time from DQS, tQH 0.38 - 0.38 - 0.38 - tCK(avg) DQ low-impedance time from CK, tLZ(DQ) -450 225 -390 195 -360 180 ps DQ high impedance time from CK, tHZ(DQ) - 225 - 195 - 180 ps Data setup time to DQS, referenced to Vih(ac) / Vil(ac) levels tDS(base) DDR3-1600 (AC175) DDR3-1866/ 2133(AC150) - - - - - - ps tDS(base) DDR3-1600 (AC150) DDR3-1866/ 2133(AC135) 10 - 68 - 53 - ps tDS(base) DDR3L-1600(AC 135) SR=1V/ns DDR3L-1866(AC 130),SR=2V/ns 25 - 70 - - - ps Data hold time from DQS, referenced to Vih(dc) / Vil(dc) levels tDH(base) DC100 DDR3-1600 (SR=1V/ns) DDR3-1866/2133 (SR=2V/ns) 45 - 70 - 55 - ps tDH(base) DC90 DDR3L-1600 (SR=1V/ns) DDR3L-1866 (SR=2V/ns) 55 - 75 - - - ps DQ and DM Input pulse width for each input tDIPW 360 - 320 - 280 - ps Data Strobe Timing DQS, differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK(avg) DQS, differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 tCK(avg) DQS, differential output high time tQSH 0.4 - 0.4 - 0.4 - tCK(avg) DQS, differential output low time tQSL 0.4 - 0.4 - 0.4 - tCK(avg) DQS, differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - tCK(avg) DQS, differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - tCK(avg) DQS, rising edge output access time from rising CK, tDQSCK -225 225 -195 195 -180 180 ps |
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