NT5CC128M8GP-EKB datasheet(145/160 Pages) NANYA

145 / 160 page

Version 2.2

145

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Parameter

Symbol

DDR3(L)-1600

DDR3(L)-1866

DDR3-2133

Unit

Min.

Max.

Min.

Max.

Min.

Max.

ODT Timings

Asynchronous RTT turn-on delay

(Power-Down with DLL frozen)

tAONPD

8.5

Asynchronous RTT turn-off delay

(Power-Down with DLL frozen)

tAOFPD

8.5

RTT turn-on

tAON

-225

225

-195

195

-180

180

RTT_Nom and RTT_WR turn-off time

from ODTLoff reference

tAOF

0.3

0.7

0.3

0.7

0.3

0.7

tCK(avg)

RTT dynamic change skew

tADC

0.3

0.7

0.3

0.7

0.3

0.7

tCK(avg)

Write Leveling Timings

First DQS/

 rising edge after

write leveling mode is programmed

tWLMRD

nCK

DQS/

 delay after write leveling mode is

programmed

tWLDQSEN

nCK

Write leveling setup time from rising CK,



crossing to rising DQS,

 crossing

tWLS

165

140

125

Write leveling hold time from rising DQS,

 crossing to rising CK,  crossing

tWLH

165

140

125

Write leveling output delay

tWLO

7.5

Write leveling output error

tWLOE

Jitter Notes

Note 1

nit “tCK(avg)” represents the actual tCK(avg) of the input clock under operation. Unit “nCK” represents one clock cycle

of the input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is

registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) +

tERR (4per), min.

Note 2

These parameters are measured from a command/address signal (CKE,

, RA, A, WE, ODT, BA0, A0, A1, etc)

transition edge to its respective clock signal (CK/

) crossing. The spec values are not affected by the amount of clock

jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the

command/address. That is, these parameters should be met whether clock jitter is present or not.

Note 3

These parameters are measured from a data strobe signal (DQS(L/U),

LU)) crossing to its respective clock signal

(CK,

) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as

these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or

not.

Note 4

These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective

data strobe signal (DQS(L/U),

LU) crossing.

Note 5

For these parameters, the DDR3(L) SDRAM device supports tnPARAM [nCK] = RU{Tparam[ns] / tCK(avg)[ns]}, which is

in clock cycles, assuming all input clock jitter specifications are satisfied.

Note 6

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR (mper), act of

the input clock, where 2 <= m <=12. (Output derating is relative to the SDRAM input clock.)

Note 7

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the

input clock. (Output deratings are relative to the SDRAM input clock.)

NT5CC128M8GP-EKB Datasheet(PDF) 145 Page - Nanya Technology Corporation.

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