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NT5CC128M8GP-EKB Datasheet(PDF) 141 Page - Nanya Technology Corporation.

Part # NT5CC128M8GP-EKB
Description  Commercial, Industrial and AutomotiveDDR3(L) 1 Gb SDRAM
PDF  160 Pages
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Manufacturer  NANYA [Nanya Technology Corporation.]
Direct Link  http://www.nanya.com
Logo NANYA - Nanya Technology Corporation.

NT5CC128M8GP-EKB Datasheet(HTML) 141 Page - Nanya Technology Corporation.

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Version 2.2
141
Nanya Technology Cooperation ©
04/2019
All Rights Reserved.
NTC Proprietary
Level: Property
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8GN / NT5CB(C)64M16GP
Parameter
Symbol
DDR3-800
DDR3(L)-1066
DDR3(L)-1333
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Power Down Timings
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
tXP
max(3tCK
,7.5ns)
-
max(3tCK
,7.5ns)
-
max(3tCK
,6ns)
-
CKE minimum pulse width
tCKE
max(3tCK
7.5ns)
-
max(3tCK
,5.625ns)
-
max(3tCK
,5.625ns)
-
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10tCK, 24ns)
tXPDLLmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
tCPDEDmax.:
-
nCK
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down
entry
tACTPDEN
tACTPDENmin.: 1
tACTPDENmax.: -
nCK
Timing of PRE or PREA command to Power
Down entry
tPRPDEN
tPRPDENmin.: 1
tPRPDENmax.: -
nCK
Timing of RD/RDA command to Power
Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
Timing of WR command to Power Down
entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR /tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
nCK
Timing of WR command to Power Down
entry (BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR /tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry (BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
nCK
Timing of REF command to Power Down
entry
tREFPDEN
tREFPDENmin.: 1
tREFPDENmax.: -
nCK
Timing of MRS command to Power Down
entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT turn on Latency
ODTLon
WL-2=CWL+AL-2
nCK
ODT turn off Latency
ODTLoff
WL-2=CWL+AL-2
nCK
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
nCK
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
ns
RTT turn-on
tAON
-400
400
-300
300
-250
250
ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
Write Leveling Timings
First DQS/
 rising edge after
write leveling mode is programmed
tWLMRD
40
-
40
-
40
-
nCK
DQS/
 delay after write leveling mode is
programmed
tWLDQSEN
25
-
25
-
25
-
nCK
Write leveling setup time from rising CK,

crossing to rising DQS,
 crossing
tWLS
325
-
245
-
195
-
ps
Write leveling hold time from rising DQS,
 crossing to rising CK,  crossing
tWLH
325
-
245
-
195
-
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns



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