GD25B256DFIS datasheet(24/82 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

7.8.

Read Data Bytes (READ 03H or 4READ 13H)

The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0), and each bit being latched-in on

the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at

a Max frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is

automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory can, therefore,

be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,

Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 10 Read Data Bytes Sequence Diagram (ADS=0)

Figure 11 Read Data Bytes Sequence Diagram (ADS=1)

Figure 12 Read Data with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

Command

03H

CS#

SCLK

High-Z

9 10

36 37 38 39 40

MSB

42 43 44 45

31 30 29

46 47

32-bit address

MSB

Data Out1

Data Out2

Command

13H

CS#

SCLK

High-Z

9 10

36 37 38 39 40

MSB

42 43 44 45

31 30 29

46 47

32-bit address

MSB

Data Out1

Data Out2

GD25B256DFIS Datasheet(PDF) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25B256DFIS Datasheet(HTML) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

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