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GD25B256DFIS Datasheet(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B256DFIS Datasheet(HTML) 32 Page - GigaDevice Semiconductor (Beijing) Inc. |
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32 / 82 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25B256D 32 Figure 22 Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0), ADS=0) Note: 1. The dummy clock number is configurable. Figure 23 Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=0) Note: 1. The dummy clock number is configurable. Command 0 1 2 3 4 5 6 7 BBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 A23-16 A15-8 A7-0 M7-4 CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK 6 7 Byte1 Byte2 Byte3 Byte4 2 0 3 1 M3-0 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 A23-16 A15-8 A7-0 M7-4 CS# 23 24 25 26 27 28 29 30 31 SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK 6 7 Byte1 Byte2 Byte3 Byte4 15 16 17 18 19 20 21 22 2 0 3 1 M3-0 |
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