GD25B256DFIS datasheet(39/82 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

use the W6-W4 setting to access the 8/16/32/64-Byte

section within any page. To exit the “Wrap Around” function and return

to normal read operation, another Set Burst with Wrap command should be issued to set W4=1.

Figure 34 Set Burst with Wrap Sequence Diagram

7.15.

Page Program (PP 02H or 4PP 12H)

The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.

The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address

Bytes and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data

that goes beyond the end of the current page are programmed from the start address of the same page (from the address

whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The

Page Program command sequence: CS# goes low  sending Page Program command  3 or 4-Byte address on SI  at

least 1 Byte data on SI  CS# goes high. If more than 256 Bytes are sent to the device, previously latched data are

discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256

data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the

other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in;

otherwise the Page Program (PP) command is not executed.

As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page

Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The

Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) command applied to a page which is protected by the Block Protect (TB, BP3, BP2, BP1, and

BP0) is not executed.

Command

77H

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

W6-W4

IO2

IO3

GD25B256DFIS Datasheet(PDF) 39 Page - GigaDevice Semiconductor (Beijing) Inc.