GD25B256DFIS datasheet(43/82 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

Figure 40 Quad Page Program with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)

7.17.

Sector Erase (SE 20H or 4SE 21H)

The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by

driving CS# low, followed by the command code, and 3-address Byte on SI. Any address inside the sector is a valid address

for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.

The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte address on SI 

CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the

Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose

duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value

of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0

when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A

Sector Erase (SE) command applied to a sector which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bit

is not executed.

Figure 41 Sector Erase Sequence Diagram (ADS=0)

Command

34H

CS#

SCLK

9 10

36 37 38 39

31 30 29

32-bit address

MSB

SI(IO0)

SO(IO1)

IO2

IO3

Byte1 Byte2

CS#

SCLK

SI(IO0)

SO(IO1)

IO2

IO3

42 43 44 45

46 47

50 51 52 53

54 55

Byte11

Byte12

Byte253

Byte256

56 57 58 59 60 61 62 63

Command

20H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

GD25B256DFIS Datasheet(PDF) 43 Page - GigaDevice Semiconductor (Beijing) Inc.

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