UPD17P133CS datasheet(47/289 Pages) NEC

47 / 289 page

CHAPTER 5

DATA MEMORY (RAM)

5.1.1 System Register (SYSREG)

The system register (SYSREG) consists of the 12 nibbles allocated at addresses 74H to 7FH in data memory. The

system register (SYSREG) is allocated independently of the banks. This means that each bank has the same system

Figure 5-2 shows the configuration of the system register.

Figure 5-2. System Register Configuration

System Register (SYSREG)

Address

74H

75H

76H

77H

78H

79H

7AH

7BH

7CH

7DH

7EH

7FH

Index register

(IX)

Data memory

row address

pointer (MP)

Name

(Symbol)

Address register

(AR)

Window

(WR)

Bank

(BANK)

General

pointer (RP)

Program

status word

(PSWORD)

5.1.2 Data Buffer (DBF)

The data buffer consists of four nibbles allocated at addresses 0CH to 0FH in BANK0 of data memory. Figure

5-3 shows the configuration of the data buffer.

Figure 5-3. Data Buffer Configuration

Data Buffer (DBF)

Address

0CH

0DH

0EH

0FH

Symbol

DBF3

DBF2

DBF1

DBF0

5.1.3 General Register (GR)

The general register consists of 16 nibbles specified by an arbitrary row address in a bank in data memory.

This arbitrary row address in a bank is pointed to by the register pointer (RP) in the system register (SYSREG).

In the case of the

µPD17120 and 17121, addresses 40H to 6EH are non-mounted areas. These areas should not

be specified as a general register.

Figure 5-4 shows the configuration of the general register (GR).

UPD17P133CS Datasheet(PDF) 47 Page - NEC

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