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UPD17P133CS Datasheet(PDF) 12 Page - NEC

Part # UPD17P133CS
Description  4-BIT SINGLE-CHIP MICROCONTROLLER
PDF  289 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD17P133CS Datasheet(HTML) 12 Page - NEC

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– vii –
LIST OF FIGURES (1/2)
Figure No.
Title
Page
3-1
Program Counter ...................................................................................................................
19
3-2
Value of the Program Counter after an Instruction Is Executed ............................................
20
3-3
Value in the Program Counter after Reset .............................................................................
20
3-4
Value in the Program Counter during Execution of a Direct Branch Instruction ....................
20
3-5
Value in the Program Counter during Execution of an Indirect Branch Instruction ................
21
3-6
Value in the Program Counter during Execution of a Direct Subroutine Call .........................
21
3-7
Value in the Program Counter during Execution of an Indirect Subroutine Call .....................
21
3-8
Value in the Program Counter during Execution of a Return Instruction ...............................
22
4-1
Program Memory Map for the
µPD17120 Subseries ............................................................
23
4-2
Direct Subroutine Call (CALL addr) ........................................................................................
26
4-3
Table Reference (MOVT DBF, @AR) .....................................................................................
27
5-1
Configuration of Data Memory ..............................................................................................
31
5-2
System Register Configuration ..............................................................................................
32
5-3
Data Buffer Configuration ......................................................................................................
32
5-4
General Register (GR) Configuration .....................................................................................
33
5-5
Port Register Configuration ...................................................................................................
33
6-1
Stack Configuration ................................................................................................................
35
7-1
Allocation of System Register in Data Memory .....................................................................
41
7-2
System Register Configuration ..............................................................................................
42
7-3
Address Register Configuration .............................................................................................
43
7-4
Address Register Used as a Peripheral Register ...................................................................
44
7-5
Window Register Configuration .............................................................................................
45
7-6
Bank Register Configuration ..................................................................................................46
7-7
Index Register and Memory Pointer Configuration ...............................................................
48
7-8
Data Memory Address Modification by Index Register and Memory Pointer .......................
48
7-9
Example of Operation When MPE=0 and IXE=0 ...................................................................
51
7-10
Example of Operation When MPE=1 and IXE=0 ...................................................................
53
7-11
Example of Operation When MPE=0 and IXE=1 ...................................................................
55
7-12
Example of Operation When MPE=0 and IXE=1 ...................................................................
57
7-13
Example of Operation When MPE=0 and IXE=1 (Array Processing) .....................................
58
7-14
General Register Pointer Configuration .................................................................................
59
7-15
General Register Configuration ..............................................................................................60
7-16
Program Status Word Configuration ......................................................................................
61
7-17
Outline of Functions of the Program Status Word ................................................................
62
8-1
General Register Configuration ..............................................................................................
70
9-1
Register File Configuration ....................................................................................................
71
9-2
Relationship Between the Register File and Data Memory ...................................................
72
9-3
Accessing the Register File Using the PEEK and POKE Instructions ....................................
74
10-1
Allocation of the Data Buffer .................................................................................................
79
10-2
Data Buffer Configuration ......................................................................................................
80
10-3
Relationship Between the Data Buffer and Peripheral Hardware ..........................................
80
11-1
Configuration of the ALU .......................................................................................................
86
12-1
Changes in port register due to execution of the CLR1 P0E1 instruction .............................
112
12-2
Input/Output Switching by Group I/O ....................................................................................
113
12-3
Bit I/O Port Control Register ..................................................................................................
114



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