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TPS65982ABZBHR Datasheet(PDF) 79 Page - Texas Instruments |
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TPS65982ABZBHR Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 121 page  P S Slave Address Wr Data Byte A A 1 7 1 8 1 1 x x 1 S Start Condition SR Repeated Start Condition Rd Read (bit value of 1) Wr Write (bit value of 0) x Field is required to have the value x A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK) P Stop Condition Master-to-Slave Slave-to-Master Continuation of protocol A Sr Unique Address Rd Byte Count = N A 1 7 1 8 1 1 S Unique Address Wr Register Number A 1 7 1 8 1 1 A P 1 A 1 Data Byte N 8 1 A Data Byte 1 8 1 A Data Byte 2 8 P S Unique Address Wr Register Number Byte Count = N Data Byte 1 A A A A 1 7 1 8 8 8 1 1 1 1 Data Byte 2 A 8 1 Data Byte N A 8 1 79 TPS65982 www.ti.com SLVSD02D – MARCH 2015 – REVISED JUNE 2019 Product Folder Links: TPS65982 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated 9.5.2.4 Unique Address Interface The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65982. The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 73 and Figure 74 show the write and read protocol for the I2C slave interface, and a key is included in Figure 75 to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part. Figure 73. I2C Unique Address Write Register Protocol Figure 74. I2C Unique Address Read Register Protocol Figure 75. I2C Read/Write Protocol Key 9.5.2.5 I2C Pin Address Setting To enable the setting of multiple I2C addresses using a single TPS65982 pin, a resistance is placed externally on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 76 shows the decoding. DEBUG_CTL1/2 are checked at the same time for the DC condition on this pin (high or low) for setting other bits of the address described previously. Note, DEBUG_CTL1/2 are GPIO and the address decoding is done by firmware in the digital core. |
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