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TPS65982ABZBHR Datasheet(PDF) 87 Page - Texas Instruments

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Part # TPS65982ABZBHR
Description  USB Type-C and USB PD Controller, Power Switch, and High-Speed Multiplexer
PDF  121 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65982ABZBHR Datasheet(HTML) 87 Page - Texas Instruments

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100 kΩ
10 kΩ
1.8 V
DC Barrel Jack Voltage
Barrel Jack Detect/
PFET Enable
Barrel Jack Detect
and PFET Enable
100 kΩ
10 kΩ
1.81 V
20 V
DC Barrel Jack
87
TPS65982
www.ti.com
SLVSD02D – MARCH 2015 – REVISED JUNE 2019
Product Folder Links: TPS65982
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
10.2.2.2.2
HD3SS460 Control and DisplayPort Configuration
The two Type-C ports in this design support DisplayPort simultaneously on both ports. When a system is not
capable of supporting video on both ports the system controller will disable DisplayPort on the second Type-C
port through I2C. Table 16 lists the DisplayPort configurations supported in the system. Table 17 lists the
summary of the TPS65982 GPIO signals control for the HD3SS460. Although the HD3SS460 is able to multiplex
the required AUX_N/P signals to the SBU_1/2 pins, they are connected through the TPS65982 for additional
support of custom alternate mode configurations.
Table 16. Supported DisplayPort Configurations
CONFIGURATION
DisplayPort ROLE
DisplayPort
PIN ASSIGNMENT
DisplayPort LANES
Configuration 1
DFP_D
Pin Assignment C
4 Lane
Configuration 2
DFP_D
Pin Assignment D
2 Lane and USB 3.1
Configuration 3
DFP_D
Pin Assignment E
4 Lane (Dongle Support)
Table 17. TPS65982 and HD3SS460 GPIO Control
TPS65982 GPIO
HD3SS460 CONTROL PIN
DESCRIPTION
GPIO_0
AMSEL
Alternate Mode Selection (DP/USB3)
GPIO_3
EN
Super Speed Mux Enable
DEBUG2
POL
Type-C Cable
10.2.2.2.3
9.3.2.3 DC Barrel Jack and Type-C PD Charging
The system is design to either charge over Type-C or from the DC barrel jack. The TPS65982 detects that the
DC barrel jack is connected to GPIOn. In the simplest form, a voltage divider could be set to the GPIO I/O level
when the DC Barrel jack voltage is present, as shown in Figure 80. A comparator circuit is recommend and used
in this design for design robustness, as shown in Figure 81.
Figure 80. DC Barrel Jack Voltage Divider
Figure 81. Barrel Jack Detect Comparator



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