68HC705JB3 datasheet(61/134 Pages) FREESCALE

61 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

16-BIT TIMER

MOTOROLA

REV 1

9-5

NOTE

To prevent interrupts from occurring between readings of the ACRH and ACRL,

set the I bit in the condition code register (CCR) before reading ACRH and clear

the I bit after reading ACRL.

9.3

INPUT CAPTURE REGISTERS

Figure 9-6. Timer Input Capture Block Diagram

The input capture function is a technique whereby an external signal (connected

to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-

ble to relate the timing of an external signal to the internal counter value, and

hence to elapsed time.

NOTE

Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0

DDR or Data Register can cause an unwanted TCAP interrupt. This can be

avoided by clearing the ICIE bit before changing the conﬁguration of PB0, and

clearing any pending interrupts before enabling ICIE.

The signal on the TCAP pin is ﬁrst directed to a schmitt trigger or a voltage

comparator as shown in Figure 9-7. Setting the TCMPE bit to “1” will enable the

comparator and the VDD/2 reference voltage.

ICRH ($0014)

16-BIT COUNTER

÷ 4

INTERNAL

(fOSC ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

INPUT CAPTURE (ICF)

RESET

CLOCK

INTERRUPT

ICRL ($0015)

TIMER STATUS REG.

$0012

$0013

INTERNAL

DATA

READ

ICRH

READ

ICRL

LATCH

BUS

EDGE

SELECT

& DETECT

LOGIC

INTERNAL

DATA

BUS

SIGNAL

CONDITIONING

PB0/

TCAP

TCMPE

(bit7 at $0E)

Freescale Semiconductor, Inc.

For More Information On This Product,

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