68HC705JB3 datasheet(64/134 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

November 5, 1998

MOTOROLA

16-BIT TIMER

MC68HC05JB3

9-8

REV 1

Reading the ICRH inhibits further captures until the ICRL is also read. Reading

the ICRL after reading the timer status register (TSR) clears the ICF ﬂag bit. does

not inhibit transfer of the free-running counter. There is no conﬂict between read-

ing the ICRL and transfers from the free-running timer counters. The input capture

registers always contain the free-running timer counter value which corresponds

to the most recent input capture.

NOTE

To prevent interrupts from occurring between readings of the ICRH and ICRL, set

the I bit in the condition code register (CCR) before reading ICRH and clear the

I bit after reading ICRL.

9.4

OUTPUT COMPARE REGISTERS

The Output Compare function is a means of generating an interrupt when the 16-

bit timer counter reaches a selected value as shown in Figure 9-10. Software

writes the selected value into the output compare registers. On every fourth inter-

nal clock cycle (every eight oscillator clock cycle) the output compare circuitry

compares the value of the free-running timer counter to the value written in the

output compare registers. When a match occurs, the output compare interrupt

ﬂag, OCF is set. A timer interrupt request to the CPU is generated if the output

compare interrupt enable is set, i.e. OCIE=1.

Port pin, PC0 is conﬁgured as the OCMP output pin when the OCMPO bit (bit7 at

$06) is set to “1”. The OCMP output reﬂects the logic of the output compare inter-

rupt ﬂag, OCF, as shown in Figure 9-10.

OCMPO — OCMP Output Enable

1 =

PC0 is OCMP pin, OCF from 16-bit timer output compare.

0 =

PC0 is standard I/O pin, from Port-C data register.

Software can use the output compare register to measure time periods, to gener-

ate timing delays, or to generate a pulse of speciﬁc duration or a pulse train of

speciﬁc frequency and duty cycle.

Writing to the OCRH before writing to the OCRL inhibits timer compares until the

OCRL is written. Reading or writing to the OCRL after reading the TSR will clear

the output compare ﬂag bit (OCF).

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DDRC

OCMPO

VROFF

DDRC3

DDRC2

DDRC1

DDRC0

$0006

reset:

00000000

Freescale Semiconductor, Inc.

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