20

DS640PP4

CS44L11

4.9

Mode Control 2 (address 0Ah)

4.9.1

Master Clock Divide Enable (MCLKDIV)

Default = 0

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other

internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK require-

ments. Refer to Tables 11, 12, 13, and Section 6.2.

4.9.2

Clock Divide (CLKDIV)

Default = 00

Function:

MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to

Tables 11, 12, 13, and Section 6.2.

76

543

21

0

mclkdiv

CLKDV1

CLKDV0

DBS

FRQSFT1

FRQSFT0

DEM1

DEM0

00

00

00

0

0

Σ

HP_A

HP_B

Left Channel

Audio Data

Right Channel

Audio Data

Channel B

Digital

Volume

Control

EQ

Channel A

Digital

Volume

Control

EQ

& Mute

& Mute

Figure 5. Dynamics Control Block Diagram