DP83261AVF datasheet(27/132 Pages) NSC

27 / 132 page

60 Control Information (Continued)

Mode Register (Mode)

The Mode Register (Mode) contains the current mode of the BMAC device

ACCESS RULES

Address

Read

Write

00h

Always

DIAG

ILB

RES

PIP

MRP

CBP

RUN

Bit

Symbol

Description

RUN

RUNStop

0 Stop Mode

All state machines return to and remain in their zero state All counters and timers are disabled The Ring

Engine transmits Idle symbols

1 Run Mode Must be in Run Mode to achieve an operational Ring

CBP

Control Bus Parity

Enables Odd Parity checking on the Control Bus Data pins (CBD7 – 0) during write

accesses

If a parity error occurs the CPE bit of the Exception Status Register is set to One and an interrupt is

generated The write data will not be deposited in the register Parity is always generated on CBD7 – 0 during

read accesses

MRP

MAC Request Parity

Enables Odd Parity checking on the MAC Request Data pins (MRD7 – 0) A parity

error causes the transmission to be aborted In REV 1 of the BMAC device MIP is always passed

transparently from PIP In all later revisions correct Odd parity is always generated on MIP

PIP

PHY Indicate Parity

Enables Odd Parity checking on the PHY Indicate Data pins (PID7 – 0) Parity errors

are treated as code violations and cause the byte in error to be replaced with Idle symbols In REV 1 of the

BMAC device Parity is passed transparently between MRP and PRP during transmission When repeating

Parity is passed transparently from PIP to PRP Odd Parity is generated for all internally generated fields In

all later revisions correct Odd Parity is always generated on the PHY Request Data pins (PRD7 – 0)

D4 – 5

RES

Reserved

ILB

Internal Loopback

Enables the internal loopback that connects PRP PRC and PRD7 – 0 to PIP PIC and

PID7 – 0 respectively When enabled the PHY Indicate Interface is ignored

Since the Ring Engine Transmitter and Receiver work as independent processes a ring can be made

operational in this mode albeit consisting only of a single MAC With an operational ring many diagnostic

tests can be performed to test out MAC level and system level diagnostics including the Beacon Process

the Claim Process Ring Engine frame generation token timers event counters transmission options test

of event detection capabilities test of addressing modes test of state machine sequencing options etc In

addition a large portion of the system interface logic can be tested such as full duplex transmission to self

within the limits of the system interface performance constraints status handling and generation etc

The same system tests can also be performed at different levels of loopback including through the various

paths within a station through the PMD interface of the PLAYER device and through the CRD device

System level tests can also be performed through the ring during normal operation

DIAG

Diagnose Mode

Enables access to all BMAC device registers When set interoperability is not

guaranteed This bit should only be set when the BMAC device is not inserted in a ring

In diagnose mode should an internal error occur the Current Receive and Transmit Status Registers are

frozen with the errored state until the internal state machine error condition is cleared (IELRRSMERR

andor IELRTSMERR)

DP83261AVF Datasheet(PDF) 27 Page - National Semiconductor (TI)

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