DP83261AVF datasheet(30/132 Pages) NSC

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60 Control Information (Continued)

Function Register (Function)

The Ring Engine performs the MAC Reset Claim Request and Beacon Request using the Function Register The Register is

initialized to Zero after a master reset A function is performed by setting the appropriate bit to One When the function is

complete the bit is cleared by the Ring Engine

ACCESS RULES

Address

Read

Write

02h

Always

RES

CLM

BCN

MCRST

RES

MARST

Bit

Symbol

Description

MARST

Master Reset

Produces the functions of an SM

CONTROL(MAC Reset) as specified by the FDDI MAC

Standard Sets all internal state machines and registers to known values

Master Reset causes the MCRST bit to be set It also clears the Mode Option Event and Mask Registers

The Timers are set to their defaults The Event Counters are not cleared

When the Master Reset function is complete MARST is cleared At this time all bits in the Function

RES

Reserved

MCRST

MAC Reset

Forces the Receiver to state R0 (Listen) and the Transmitter to state T0 (Idle)

TNEG (Registers 98 – 9B) is not loaded with TMAX (this operation can be performed as part of the MAC

Reset Request actions by writing to TNEG before the MAC Reset is initiated)

MCRST takes precedence over bits D3 (BCN) and D4 (CLM) but does not clear these bits

A MAC Reset that occurs while a frame is being transmitted will cause the frame to be aborted Frames

without the Frame Status are not transmitted by the Ring Engine Whenever the byte with the Ending

Delimiter is transmitted valid frame status is transmitted as well If a MAC Reset occurs during the byte

where the Ending Delimiter and E Indicator should be transmitted it will not be transmitted If a MAC Reset

occurs on the cycle where the A and C Indicators are transmitted they will still be transmitted

BCN

Beacon Request

Produces the functions of an SM

CONTROLrequest (Beacon) as required by the FDDI

MAC Standard The Ring Engine Transmitter is forced to enter the Beacon State Beacon frames are then

transmitted until the Beacon Process completes The Beacon Process will not complete if OptionIRRe1

Beacon frames are generated by the Ring Engine unless an Immediate Beacon Request is present at the

MAC Request Interface and a frame is ready to be transmitted Even with an External Immediate Beacon

Request the Ring Engine transmits at least one Beacon frame before the Beacon frames from the MAC

Request Interface are transmitted

If an external Beacon frame is to be transmitted the Beacon frame should first be set up then the request

should be given to the MAC Request Interface and then bit BCN should be set to One

Writing to this bit also sets bit D2 (MCRST) This bit is cleared on entry to the Beacon state If both bits D3

(BCN) and D4 (CLM) are set bit D3 takes precedence

CLM

Claim Request

Produces the functions equivalent to an SM

CONTROLrequest (Claim) and causes entry

to the Claim State The Ring Engine Transmitter is forced to enter the Claim State unless the Transmitter is

in the Beacon State or bit BCN is set to One Claim frames are then transmitted until the Claim Process

completes The Claim Process will not complete if OptionITRe1

A Claim Request is honored immediately from any state except the Beacon state It is honored in the

Beacon state when a My

Beacon returns Claim requests are honored even when OptionIRRe1

Claim frames are generated by the Ring Engine unless an Immediate Claim Request is available at the MAC

Request Interface Even with an Immediate Claim Request at the interface the Ring Engine transmits at

least one Claim frame before the Claim frames from the MAC Request Interface are transmitted

If an external Claim frames is to be transmitted the Claim frame should first be set up then the request

should be given to the MAC Request Interface before the CLM bit is set to One

The Claim bit is reset upon entry to the Claim or Beacon state

D5 – 7

RES

Reserved

DP83261AVF Datasheet(PDF) 30 Page - National Semiconductor (TI)

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