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845GL Datasheet(PDF) 65 Page - Intel Corporation |
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845GL Datasheet(HTML) 65 Page - Intel Corporation |
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65 / 193 page ![]() Intel® 82845G/82845GL/82845GV GMCH Datasheet 65 Register Description At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. As an example, consider BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus. The host then does a write of the same address, which is directed to main memory. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Figure 3-4 and Table 3-2 show the PAM registers and the associated attribute bits. For details on overall system address mapping scheme, refer to Chapter 5. Figure 3-4. PAM Register Attributes Table 3-2. PAM Register Attributes PAM Reg Attribute Bits Memory Segment Comments Offset PAM0[3:0] Reserved 90h PAM0[7:4] R R WE RE 0F0000h–0FFFFFh BIOS Area 90h PAM1[3:0] R R WE RE 0C0000h–0C3FFFh ISA Add-on BIOS 91h PAM1[7:4] R R WE RE 0C4000h–0C7FFFh ISA Add-on BIOS 91h PAM2[3:0] R R WE RE 0C8000h–0CBFFFh ISA Add-on BIOS 92h PAM2[7:4] R R WE RE 0CC000h–0CFFFFh ISA Add-on BIOS 92h PAM3[3:0] R R WE RE 0D0000h–0D3FFFh ISA Add-on BIOS 93h PAM3[7:4] R R WE RE 0D4000h–0D7FFFh ISA Add-on BIOS 93h PAM4[3:0] R R RE 0D8000h–0DBFFFh ISA Add-on BIOS 94h PAM4[7:4] R R WE RE 0DC000h–0DFFFFh ISA Add-on BIOS 94h PAM5[3:0] R R WE RE 0E0000h–0E3FFFh BIOS Extension 95h PAM5[7:4] R R WE RE 0E4000h–0E7FFFh BIOS Extension 95h PAM6[3:0] R R WE RE 0E8000h–0EBFFFh BIOS Extension 96h PAM6[7:4] R R WE RE 0EC000h–0EFFFFh BIOS Extension 96h RE WE RE R R WE R R 7 6 5432 10 PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved 96h 95h 94h 93h 92h 91h 90h Offset |
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