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845GL Datasheet(PDF) 54 Page - Intel Corporation |
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845GL Datasheet(HTML) 54 Page - Intel Corporation |
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54 / 193 page ![]() Register Description 54 Intel® 82845G/82845GL/82845GV GMCH Datasheet 3.5.1.8 MLT —Master Latency Timer Register (Device 0) Address Offset: 0Dh Default Value: 00h Access: RO Size: 8 bits Device 0 in the GMCH is not a PCI master. Therefore this register is not implemented. 3.5.1.9 HDR —Header Type Register (Device 0) Address Offset: 0Eh Default Value: 00h Access: RO Size: 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit Description 7:0 Reserved. Bit Description 7:0 PCI Header (HDR). This field always returns 0 to indicate that the GMCH is a single function device with standard header layout. |
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