845GL datasheet(86/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2.16

SSTS1—Secondary Status Register (Device 1)

Address Offset:

1Eh

Default Value:

02A0h

Access:

RO, R/WC

Size:

16 bits

SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with

secondary side (i.e., PCI_B/AGP side) of the “virtual” PCI-to-PCI bridge embedded within the

GMCH.

Bit

Description

Detected Parity Error (DPE)—R/WC.

0 = Software sets DPE1 to 0 by writing a 1 to this bit.

1 = Indicates GMCH’s detection of a parity error in the address or data phase of PCI_B/AGP bus

transactions.

Received System Error (RSE)—RO.

Hardwired to 0. GMCH does not have an SERR# signal pin on

the AGP interface.

Received Master Abort Status (RMAS)—R/WC.

0 = Software resets this bit to 0 by writing a 1 to it.

1 = GMCH terminated a Host-to-PCI_B/AGP with an unexpected master abort.

Received Target Abort Status (RTAS)—R/WC.

0 = Software resets RTAS1 to 0 by writing a 1 to it.

1 = GMCH-initiated transaction on PCI_B/AGP is terminated with a target abort.

Signaled Target Abort Status (STAS)—RO.

Hardwired to a 0. GMCH does not generate target

abort on PCI_B/AGP.

10:9

DEVSEL# Timing (DEVT)—RO.

Hardwired to a 00. This field indicates the timing of the DEVSEL#

signal when the GMCH responds as a target on PCI_B/AGP. It is hardwired to 01b (medium) to

indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.

Master Data Parity Error Detected (DPD)—RO.

Hardwired to 0. GMCH does not implement

G_PERR# signal on PCI_B.

Fast Back-to-Back (FB2B)—RO.

Hardwired to 1. GMCH, as a target, supports fast back-to-back

transactions on PCI_B/AGP.

Reserved.

66/60 MHz Capability (CAP66)—RO.

Hardwired to 1. Indicates that the AGP/PCI_B bus is capable

of 66 MHz operation.

4:0

Reserved.

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