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845GL Datasheet(PDF) 88 Page - Intel Corporation |
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845GL Datasheet(HTML) 88 Page - Intel Corporation |
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88 / 193 page ![]() Register Description 88 Intel® 82845G/82845GL/82845GV GMCH Datasheet 3.5.2.18 MLIMIT1—Memory Limit Address Register (Device 1) Address Offset: 22–23h Default Value: 0000h Access: RO, R/W Size: 16 bits This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom four bits of this register are read-only and return zeros when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI_B/AGP address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges (typically graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved processor-AGP memory access performance. Note: Configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). There is no provision in the GMCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. Bit Description 15:4 Memory Address Limit (MLIMIT). Corresponds to A[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 1 bridge to AGP/ PCI_B. 3:0 Reserved. |
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