845GL datasheet(114/193 Pages) INTEL

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Functional Description

114

Intel® 82845G/82845GL/82845GV GMCH Datasheet

4.3.1.6

4X AGP Protocol

In addition to the 1X and 2X AGP protocol, the GMCH supports 4X AGP read and write data

transfers and 4X sideband address generation. The 4X operation is compliant with the 4X AGP

specification as currently described in the Accelerated Graphics Port Interface Specification,

Revision 2.0.

The GMCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP Status

initialization, the GMCH performs AGP read and write data transactions using 4X protocol. This

bit is not dynamic. Once this bit is set during initialization, the data transfer rate will not change.

The 4X data transfer protocol provides 1.06 GB/s transfer rates. The control signal protocol for the

4X data transfer protocol is identical to 1X/2X protocol. In 4X mode, 16 bytes of data are

transferred during each 66 MHz clock period. The minimum throttle-able block size remains four,

66 MHz clocks which means 64 bytes of data is transferred per block. Three additional signal pins

are required to implement the 4X data transfer protocol. These signal pins are complementary data

transfer strobes for the AD bus (2) and the SBA bus (1).

4.3.1.7

Fast Writes

The Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target.

This type of access is required to pass data/control directly to the AGP master instead of placing

the data into main memory and then having the AGP master read the data. For 1X transactions, the

protocol simply follows the PCI Local Bus Specification, Revision 2.2. However, for higher speed

transactions (2X or 4X), FW transactions follow a combination for PCI and AGP bus protocols for

data movement.

4.3.1.8

AGP 1.5 V Connector

GMCH’s AGP buffers only support 1.5 V operation. Therefore, 845G chipsets only support 1.5 V

AGP connectors.

845GL Datasheet(PDF) 114 Page - Intel Corporation