RA4W1 datasheet(68/105 Pages) RENESAS

68 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 68 of 105

Mar 31, 2020

RA4W1 Datasheet

2. Electrical Characteristics

Figure 2.57

I2C bus interface input/output timing

2.3.11

CLKOUT Timing

Note 1.

When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and

the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to

55%.

Note 2.

When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division

ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).

Note 3.

The voltage for VCC_RF when CLKOUT_RF pin is to be used is between 3.0 V and 3.6 V.

Table 2.39

CLKOUT timing

Parameter

Symbol

Min

Max

Unit*1

Test conditions

CLKOUT

CLKOUT pin output cycle*1

VCC = 2.7 V or above

tCcyc

62.5

Figure 2.58

VCC = 1.8 V or above

125

CLKOUT pin high pulse width*2

VCC = 2.7 V or above

tCH

VCC = 1.8 V or above

CLKOUT pin low pulse width*2

VCC = 2.7 V or above

tCL

VCC = 1.8 V or above

CLKOUT pin output rise time

VCC = 2.7 V or above

tCr

-12

VCC = 1.8 V or above

CLKOUT pin output fall time

VCC = 2.7 V or above

tCf

-12

VCC = 1.8 V or above

CLKOUT_RF*3

CLKOUT_RF pin output cycle

tCRFcyc

250

Figure 2.59

CLKOUT_RF pin high pulse width

tCRFH

100

CLKOUT_RF pin low pulse width

tCRFL

100

CLKOUT_RF pin output rise time

tCRFr

-5

CLKOUT_RF pin output fall time

tCRFf

-5

SDA0, SDA1

SCL0, SCL1

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Sr*1

Note 1.

S, P, and Sr indicate the following conditions.

S: Start condition

P: Stop condition

Sr: Restart condition

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