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RA4W1 Datasheet(PDF) 94 Page - Renesas Technology Corp |
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RA4W1 Datasheet(HTML) 94 Page - Renesas Technology Corp |
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94 / 105 page  R01DS0359EJ0100 Rev.1.00 Page 94 of 105 Mar 31, 2020 RA4W1 Datasheet 2. Electrical Characteristics Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. 2.16 Joint Test Action Group (JTAG) Table 2.67 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 3.6 V, Ta = –40 to +85°C Parameter Symbol FCLK = 4 MHz FCLK = 8 MHz Unit Min Typ Max Min Typ Max Programming time 1-byte tDP1 - 94.7 886 - 89.3 849 μs Erasure time 1-KB tDE1K - 9.59 299 - 8.29 273 ms Blank check time 1-byte tDBC1 - - 56.2 - - 52.5 μs 1-KB tDBC1K - - 2.17 - - 1.51 ms Suspended time during erasing tDSED - - 23.0 - - 21.7 μs Data flash STOP recovery time tDSTOP 720 - - 720 - - ns Table 2.68 JTAG (debug) characteristics (1) Conditions: VCC = 2.4 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 80 - - ns Figure 2.75 TCK clock high pulse width tTCKH 35 - - ns TCK clock low pulse width tTCKL 35 - - ns TCK clock rise time tTCKr -- 5 ns TCK clock fall time tTCKf -- 5 ns TMS setup time tTMSS 16 - - ns Figure 2.76 TMS hold time tTMSH 16 - - ns TDI setup time tTDIS 16 - - ns TDI hold time tTDIH 16 - - ns TDO data delay time tTDOD - - 70 ns Table 2.69 JTAG (debug) characteristics (2) Conditions: VCC = 1.8 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 250 - - ns Figure 2.75 TCK clock high pulse width tTCKH 120 - - ns TCK clock low pulse width tTCKL 120 - - ns TCK clock rise time tTCKr -- 5 ns TCK clock fall time tTCKf -- 5 ns TMS setup time tTMSS 50 - - ns Figure 2.76 TMS hold time tTMSH 50 - - ns TDI setup time tTDIS 50 - - ns TDI hold time tTDIH 50 - - ns TDO data delay time tTDOD - - 150 ns |
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