DS280DF810ABVT datasheet(28/51 Pages) TI1

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DS280DF810

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over

equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit

error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

•

Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.

•

With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this

mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow these steps below within the desired channel register set:

Table 4. Eye Opening Monitor Full Eye Capture Instructions

STEP

OPERATION

VALUE

DESCRIPTION

0x67[5]

Write

Disable lock EOM lock monitoring

0x2C[6]

Write

Set the desired EOM vertical range

0x11[7:6]

Write

2'b--

0x11[5]

Write

Power on the EOM

0x24[7]

Write

Enable fast EOM

0x24[0]

0x25

0x26

Read

Begin read out of the 64 x 64 array, discard first 4 words

Ch reg 0x24[0] is self-clearing.

0x25 is the MSB of the 16-bit word

0x26 is the LSB of the 16-bit word

0x25

Read

Continue reading information until the 64 x 64 array is

complete.

0x26

0x67[5]

Write

Return the EOM to its original state. Undo steps 1-4

0x2C[6]

Write

0x11[5]

Write

0x24[7]

Write

8.3.2.4 Interrupt Signals

The DS280DF810 can be configured to report different events as interrupt signals. These interrupt signals do not

impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in

the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that

interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once

the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The

DS280DF810 will report the occurrence of an interrupt through the INT_N pin. The INT_N pin is an open drain

output that will pull the line low when an interrupt signal is triggered.

Note that all available interrupts are disabled by default. Users must activate the various interrupts before they

can be used.

The interrupts available in the DS280DF810 are:

•

CDR loss of lock

•

CDR locked

•

Signal detect loss

•

Signal detected

•

PRBS pattern checker bit error detected

•

HEO/VEO threshold violation

When an interrupt occurs, share register 0x08 reports which channel generated the interrupt request. Users can

then select the channels that generated the interrupt request and service the interrupt by reading the appropriate

interrupt status bits in the corresponding channel registers. For more information on reading interrupt status, refer

to the DS280DF810 Programming Guide.

DS280DF810ABVT Datasheet(PDF) 28 Page - Texas Instruments

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