DS280DF810ABVT datasheet(29/51 Pages) TI1

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DS280DF810

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SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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8.4 Device Functional Modes

8.4.1 Supported Data Rates

The DS280DF810 supports a wide range of input data rates, including divide-by-2 and divide-by-4 sub-rates. The

supported data rates are listed in Table 5. Refer to the DS280DF810 Programming Guide for information on

configuring the DS280DF810 for different data rates.

Table 5. Supported Data Rates

DATA RATE RANGE

DIVIDER

CDR MODE

COMMENT

MIN

MAX

≥ 20.2 Gbps

≤ 28.4 Gbps

Enabled

≥ 10.1 Gbps

≤ 14.2 Gbps

Enabled

> 7.1 Gbps

< 10.1 Gbps

N/A

Disabled

Output jitter will be higher

with CDR disabled.

≥ 5.05 Gbps

≤ 7.1 Gbps

Enabled

≥ 1.25 Gbps

< 5.05 Gbps

N/A

Disabled

Output jitter will be higher

with CDR disabled.

8.4.2 SMBus Master Mode

SMBus master mode allows the DS280DF810 to program itself by reading directly from an external EEPROM.

When using the SMBus master mode, the DS280DF810 will read directly from specific location in the external

EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific

guidelines:

•

Maximum EEPROM size is 2048 Bytes

•

Minimum EEPROM size for a single DS280DF810 with individual channel configuration is 595 Bytes (3 base

header bytes + 12 address map bytes + 8 x 72 channel register bytes + 2x2 share register bytes; bytes are

defined to be 8-bits)

•

Set ENSMB = Float, for SMBus master mode

•

The external EEPROM device address byte must be 0xA0

•

The external EEPROM device must support 400 kHz operation at 2.5 V or 3.3 V supply

•

Set the SMBus address of the DS280DF810 by configuring the ADDR0 and ADDR1 pins

When loading multiple DS280DF810 devices from the same EEPROM, use these guidelines to configure the

devices:

•

Configure the SMBus addresses for each DS280DF810 to be sequential. The first device in the sequence

must have an address of 0x30

•

Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they

do not compete for the EEPROM at the same time.

•

If all of the DS280DF810 devices share the same EEPROM channel and share register settings, configure

the common channel bit in the base header to 1. With common channel configuration enabled, each

DS280DF810 device will configure all 8 channels with the same settings.

When loading a single DS280DF810 from an EEPROM, use these guidelines to configure the device:

•

Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit

to 1 to load the same configuration settings to all channels.

•

When configuring individual channels, a 1024 Byte or 2048 Byte EEPROM must be used.

•

If there are more than three DS280DF810 devices on a PCB that require individual channel configuration,

then each device must have its own EEPROM.

8.4.3 Device SMBus Address

The DS280DF810’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is

read on power up, after the internal power-on reset signal is de-asserted. The ADDR[1:0] pins are four-level

LVCMOS IOs, which provides for 16 unique SMBus addresses. The four levels are achieved by pin strap options

as follows:

•

0: 1 k

Ω to GND

DS280DF810ABVT Datasheet(PDF) 29 Page - Texas Instruments

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