CS47L15 datasheet(52/279 Pages) CIRRUS

52 / 279 page

DS1137F2

CS47L15

4.3 Digital Core

The hexadecimal numbers in Fig. 4-19 indicate the corresponding x_SRCn setting for selection of that signal as an input

to another digital-core function.

The sample rate for the DRC function is configured using FX_RATE; see Table 4-24. Note that the EQ, DRC, and LHPF

functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the DRC

signal paths to any signal chain that is configured for a different sample rate.

The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields

must be cleared before writing a new value to FX_RATE. A minimum delay of 125

s must be allowed between clearing

the x_SRCn fields and writing to FX_RATE. See Table 4-24 for details.

The DRC functions are enabled using the control registers described in Table 4-14.

The following description of the DRC is applicable to each of the DRCs. The associated control fields are described in

Table 4-16 and Table 4-17 for DRC1 and DRC2 respectively.

4.3.5.1 DRC Compression, Expansion, and Limiting

The DRC supports two different compression regions, separated by a knee at a specific input amplitude. In the region

above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope

DRCn_LO_COMP applies. Note that n identifies the applicable DRC 1 or 2.

The DRC also supports a noise-gate region, where low-level input signals are heavily attenuated. This function can be

enabled or disabled according to the application requirements. The DRC response in this region is defined by the

expansion slope DRCn_NG_EXP.

For additional attenuation of signals in the noise-gate region, an additional knee can be defined (shown as Knee 2 in

Fig. 4-20). When this knee is enabled, this introduces an infinitely steep drop-off in the DRC response pattern between the

DRCn_LO_COMP and DRCn_NG_EXP regions.

The overall DRC compression characteristic in steady state (i.e., where the input amplitude is near constant) is shown in

Fig. 4-20.

Table 4-14. DRC Enable

Bit

Label

Default

Description

R3712 (0x0E80)

DRC1_ctrl1

DRC1L_ENA

DRC1 (left) enable

0 = Disabled

1 = Enabled

DRC1R_ENA

DRC1 (right) enable

0 = Disabled

1 = Enabled

R3720 (0x0E88)

DRC2_ctrl1

DRC2L_ENA

DRC2 (left) enable

0 = Disabled

1 = Enabled

DRC2R_ENA

DRC2 (right) enable

0 = Disabled

1 = Enabled

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