CS47L15 datasheet(16/279 Pages) CIRRUS

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DS1137F2

CS47L15

3 Characteristics and Specifications

Table 3-11. Miscellaneous Characteristics

Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;

1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.

Parameter

Min

Typ

Max

Units

Microphone bias

(MICBIAS1A,

MICBIAS1B,

MICBIAS1C) 1

1.No capacitor on MICBIAS1x. In Regulator Mode, it is required that VMICVDD – VMICBIAS > 200 mV.

Minimum Bias Voltage 2

Maximum Bias Voltage

Bias Voltage output step size

Bias Voltage accuracy

2.Regulator Mode (MICB1_BYPASS = 0), Load current

 1.0 mA.

—

–5%

1.5

2.8

0.1

—

+5%

Bias Current 3

3.Bias current and load capacitance specifications are for the sum of all enabled MICBIAS1x outputs.

Regulator Mode (MICB1_BYPASS = 0), VMICVDD – VMICBIAS >200 mV

Bypass Mode (MICBn_BYPASS = 1)

—

2.4

5.0

Output Noise Density

Regulator Mode (MICB1_BYPASS = 0), MICB1_LVL = 0x4,

Load current = 1 mA, Measured at 1 kHz

—50

—

nV/

Hz

Integrated noise voltage

Regulator Mode (MICB1_BYPASS = 0), MICB1_LVL = 0x4,

Load current = 1 mA, 100 Hz to 7 kHz, A-weighted

—5

—

VRMS

PSRR (DBVDD, CPVDD, AVDD), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

100

—

PSRR (MICVDD), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

PSRR (DCVDD), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

100

—

PSRR (SPKVDD), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

100

—

Load capacitance 3

Regulator Mode (MICB1_BYPASS = 0), MICB1_EXT_CAP = 0

Regulator Mode (MICB1_BYPASS = 0), MICB1_EXT_CAP = 1

—

0.1

—

1.0

F

Output discharge resistance

MICBnx_ENA = 0, MICBnx_DISCH = 1

—



General-purpose

switch 4

4.The GPSWN pin voltage must not exceed GPSWP + 0.3 V. See Table 3-2 for voltage limits applicable to the GPSWP and GPSWN pins.

Switch resistance

Switch closed, I = 1 mA

Switch open

—

100

—



External

Accessory

Detect

Headphone detection load impedance range:

Detection via HPOUTL (HPD_SENSE_SEL = 100) or

HPOUTR (HPD_SENSE_SEL = 101)

HPD_IMPEDANCE_RANGE = 01

HPD_IMPEDANCE_RANGE = 10

HPD_IMPEDANCE_RANGE = 11

—

1000



Headphone detection load impedance range:

Detection via MICDETn or JACKDETn pins

400

—

6000



Headphone detection accuracy:

(HPD_DACVAL, HPD_SENSE_SEL = 100 or 101)

HPD_IMPEDANCE_RANGE = 01

HPD_IMPEDANCE_RANGE = 10

HPD_IMPEDANCE_RANGE = 11

–10

–5

–10

—

+10

Headphone detection accuracy (HPD_LVL, HPD_SENSE_SEL = 0XX or 11X)

–20

—

+20

Microphone impedance detection range:

(MICD1_ADC_MODE = 0, 2.2 k

 ±2% MICBIAS resistor. 5

5.These characteristics assume no other component is connected to MICDETn.

for MICD1_LVL[0] = 1

for MICD1_LVL[1] = 1

for MICD1_LVL[2] = 1

for MICD1_LVL[3] = 1

for MICD1_LVL[8] = 1

110

210

360

—

180

290

680



Jack-detection input threshold voltage

(JACKDETn)

Detection on JACKDET1, Jack insertion

Detection on JACKDET1, Jack removal

Detection on JACKDET2, Jack insertion

Detection on JACKDET2, Jack removal

—

0.9

1.65

0.27

0.9

—

Pull-up resistance (JACKDETn)—

—



Frequency-Lock

ed Loop (FLL1)

Output frequency

FLL output as SYSCLK source

FLL output as DSPCLK source

135

—

98.3

150

MHz

Lock Time

FREF =32 kHz, FOUT (DSPCLK source) = 147.456 MHz

FREF =12MHz, FOUT (DSPCLK source) = 147.456 MHz

—

RESET pin input RESET input pulse width 6

6.To trigger a hardware reset, the RESET input must be asserted for longer than this duration.

1—

—

s

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