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CS47L15 Datasheet(PDF) 97 Page - Cirrus Logic |
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CS47L15 Datasheet(HTML) 97 Page - Cirrus Logic |
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97 / 279 page  DS1137F2 97 CS47L15 4.5 DSP Peripheral Control 4.5.1.8 Event Logger Input Sources A list of the valid input sources for the event loggers is provided in Table 4-35. The EDGE type noted is coded as S (single edge) or D (dual edge). Note that a single-edge input source only provides valid input to the event logger in the default (rising edge triggered) polarity. Caution is advised when enabling IRQ1 or IRQ2 as an input source for the event loggers; a recursive loop, where the IRQn signal is also an output from the same event logger, must be avoided. Base address +0xB2 EVENTLOGn_FIFO12_TIME 31:0 EVENTLOGn_FIFO12_ TIME[31:0] 0x0000 _0000 Event Log FIFO Index 12 Time Base address +0xB4 EVENTLOGn_FIFO13_ READ 12 EVENTLOGn_FIFO13_POL 0 Event Log FIFO Index 13 polarity 0 = Rising edge, 1 = Falling edge 8:0 EVENTLOGn_FIFO13_ID[8:0] 0x000 Event Log FIFO Index 13 source 1 Base address +0xB6 EVENTLOGn_FIFO13_TIME 31:0 EVENTLOGn_FIFO13_ TIME[31:0] 0x0000 _0000 Event Log FIFO Index 13 Time Base address +0xB8 EVENTLOGn_FIFO14_ READ 12 EVENTLOGn_FIFO14_POL 0 Event Log FIFO Index 14 polarity 0 = Rising edge, 1 = Falling edge 8:0 EVENTLOGn_FIFO14_ID[8:0] 0x000 Event Log FIFO Index 14 source 1 Base address +0xBA EVENTLOGn_FIFO14_TIME 31:0 EVENTLOGn_FIFO14_ TIME[31:0] 0x0000 _0000 Event Log FIFO Index 14 Time Base address +0xBC EVENTLOGn_FIFO15_ READ 12 EVENTLOGn_FIFO15_POL 0 Event Log FIFO Index 15 polarity 0 = Rising edge, 1 = Falling edge 8:0 EVENTLOGn_FIFO15_ID[8:0] 0x000 Event Log FIFO Index 15 source 1 Base address +0xBE EVENTLOGn_FIFO15_TIME 31:0 EVENTLOGn_FIFO15_ TIME[31:0] 0x0000 _0000 Event Log FIFO Index 15 Time 1.See Table 4-35 for valid channel source selections Table 4-35. Event Logger Input Sources ID Description Edge ID Description Edge ID Description Edge 3 irq1 D 165 dsp_irq6 S 261 gpio6 D 4 irq2 D 166 dsp_irq7 S 262 gpio7 D 9 sysclk_fail S 167 dsp_irq8 S 263 gpio8 D 24 fll1_lock D 168 dsp_irq9 S 264 gpio9 D 27 fll_ao_lock D 169 dsp_irq10 S 265 gpio10 D 32 frame_start_g1r1 S 170 dsp_irq11 S 266 gpio11 D 33 frame_start_g1r2 S 171 dsp_irq12 S 267 gpio12 D 34 frame_start_g1r3 S 172 dsp_irq13 S 268 gpio13 D 80 hpdet S 173 dsp_irq14 S 269 gpio14 D 88 micdet1 S 174 dsp_irq15 S 270 gpio15 D 89 micdet2 S 175 dsp_irq16 S 320 Timer1 S 96 jd1_rise S 176 hp1l_sc S 321 Timer2 S 97 jd1_fall S 177 hp1r_sc S 336 event1_not_empty S 98 jd2_rise S 178 hp2l_sc S 337 event2_not_empty S 99 jd2_fall S 179 hp2r_sc S 352 event1_full S 100 micd_clamp_rise S 182 spkoutl_short D 353 event2_full S 101 micd_clamp_fall S 224 spk_shutdown D 368 event1_wmark S 128 drc1_sig_det D 225 spk_overheat S 369 event2_wmark S 129 drc2_sig_det D 226 spk_overheat_warn S 384 dsp1_dma S 160 dsp_irq1 S 256 gpio1 D 416 dsp1_start1 S 161 dsp_irq2 S 257 gpio2 D 432 dsp1_start2 S 162 dsp_irq3 S 258 gpio3 D 448 dsp1_start S 163 dsp_irq4 S 259 gpio4 D 464 dsp1_busy D 164 dsp_irq5 S 260 gpio5 D Table 4-34. Event Logger (EVENTLOGn) Control (Cont.) Register Address Bit Label Default Description |
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