CS47L15 datasheet(88/279 Pages) CIRRUS

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DS1137F2

CS47L15

4.4 DSP Firmware Control

4.4.6

DSP Debug Support

General-purpose registers are provided for the DSP. These have no assigned function and can be used to assist in

algorithm development.

The JTAG interface provides test and debug access to the CS47L15, as described in Section 4.17. The JTAG interface

clock can be enabled for the DSP core using DSP1_DBG_CLK_ENA. Note that, when the JTAG interface is used to

access the DSP core, the DSP1_CORE_ENA bit must also be set.

The DSP1_LOCK_ERR_STS bit indicates that the DSP attempted to write to a locked register address. The DSP1_

ADDR_ERR_STS bit indicates that the DSP attempted to access an invalid memory address (i.e., an address whose

contents are undefined). Once set, these bits remain set until a 1 is written to DSP1_ERR_CLEAR.

The DSP1_PMEM_ERR_ADDR and DSP1_XMEM_ERR_ADDR fields contain the program memory and X-data memory

addresses associated with a locked register address error condition. If DSP1_LOCK_ERR_STS is set, these fields

correspond to the first-detected locked register address error. Note that no subsequent error event can be reported in

these fields until the DSP1_LOCK_ERR_STS is cleared.

Note: The DSP1_PMEM_ERR_ADDR value is the prefetched address of a code instruction that has not yet been

executed; it does not point directly to the instruction that caused the error.

The DSP1_BUS_ERR_ADDR field indicates the register/memory address that resulted in a register-access error. The

field relates either to a locked register address error or to an invalid memory address error, as follows:

• If DSP1_LOCK_ERR_STS is set, the DSP1_BUS_ERR_ADDR value corresponds to the first-detected locked

STS is cleared.

• If DSP1_ADDR_ERR_STS is set, and DSP1_LOCK_ERR_STS is clear, the DSP1_BUS_ERR_ADDR field

corresponds to the most recent invalid memory address error.

• If the DSP1_LOCK_ERR_STS and DSP1_ADDR_ERR_STS are both clear, the DSP1_BUS_ERR_ADDR field is

undefined.

Note: The DSP1_BUS_ERR_ADDR value is coded using a byte-referenced address, so the actual register address is

equal to DSP1_BUS_ERR_ADDR / 2. If the register-access error is the result of an attempt to access the virtual

DSP registers, a register address of 0 is reported.

If the DSP1_ERR_PAUSE bit is set, the DSP code execution stops immediately on detection of a locked register address

error. This enables debug information to be retrieved from the DSP core during code development. In this event, code

execution can be restarted by clearing the DSP1_ERR_PAUSE bit. Alternatively, the DSP core can restarted by clearing

and setting DSP1_CORE_ENA (described in Section 4.4.3.3).

R5634 (0x1602)

ADSP2_IRQ2

DSP_IRQ6

DSP IRQ6. Write 1 to trigger the DSP_IRQ6_EINTn interrupt.

DSP_IRQ5

DSP IRQ5. Write 1 to trigger the DSP_IRQ5_EINTn interrupt.

R5635 (0x1603)

ADSP2_IRQ3

DSP_IRQ8

DSP IRQ8. Write 1 to trigger the DSP_IRQ8_EINTn interrupt.

DSP_IRQ7

DSP IRQ7. Write 1 to trigger the DSP_IRQ7_EINTn interrupt.

R5636 (0x1604)

ADSP2_IRQ4

DSP_IRQ10

DSP IRQ10. Write 1 to trigger the DSP_IRQ10_EINTn interrupt.

DSP_IRQ9

DSP IRQ9. Write 1 to trigger the DSP_IRQ9_EINTn interrupt.

R5637 (0x1605)

ADSP2_IRQ5

DSP_IRQ12

DSP IRQ12. Write 1 to trigger the DSP_IRQ12_EINTn interrupt.

DSP_IRQ11

DSP IRQ11. Write 1 to trigger the DSP_IRQ11_EINTn interrupt.

R5638 (0x1606)

ADSP2_IRQ6

DSP_IRQ14

DSP IRQ14. Write 1 to trigger the DSP_IRQ14_EINTn interrupt.

DSP_IRQ13

DSP IRQ13. Write 1 to trigger the DSP_IRQ13_EINTn interrupt.

R5639 (0x1607)

ADSP2_IRQ7

DSP_IRQ16

DSP IRQ16. Write 1 to trigger the DSP_IRQ16_EINTn interrupt.

DSP_IRQ15

DSP IRQ15. Write 1 to trigger the DSP_IRQ15_EINTn interrupt.

Table 4-32. DSP Interrupts (Cont.)

Bit

Label

Default

Description

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