RX113 datasheet(87/131 Pages) RENESAS

87 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 87 of 131

Sep 07, 2020

RX113 Group

5. Electrical Characteristics

Note 1. tPcyc: PCLK cycle

Table 5.32

Timing of On-Chip Peripheral Modules (3)

Conditions: 1.8 V

≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,

Ta = –40 to +105°C, C = 30 pF

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

65536

tPcyc

Figure 5.42

SCK clock cycle input (slave)

—

tPcyc

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKr, tSPCKf

—20

Data input setup time (master)

2.7 V or above

tSU

—

Figure 5.43,

Figure 5.45

1.8 V or above

—

Data input setup time (slave)

—

Data input hold time

—

SS input setup time

tLEAD

3—

tSPcyc

SS input hold time

tLAG

3—

tSPcyc

Data output delay time (master)

tOD

—40

Data output delay time (slave)

2.7 V or above

—

1.8 V or above

—

100

Data output hold time (master)

2.7 V or above

tOH

–10

—

1.8 V or above

–20

—

Data output hold time (slave)

–10

—

Data rise/fall time

tDr, tDf

—20

SS input rise/fall time

tSSLr, tSSLf

—20

Slave access time

tSA

—6

tPcyc

Figure 5.47,

Figure 5.48

Slave output release time

tREL

—6

tPcyc

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