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UPD17P136ACT Datasheet(PDF) 156 Page - NEC |
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UPD17P136ACT Datasheet(HTML) 156 Page - NEC |
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156 / 292 page ![]() CHAPTER 13 PERIPHERAL HARDWARE 137 (c) Successive mode A/D conversion timing Figure 13-16 shows the A/D conversion timing in the successive mode. Figure 13-19. A/D Conversion Timing in the Continuous Mode Caution Sampling is executed eight times while A/D conversion is performed once. Therefore, if the analog input voltage changes substantially during A/D conversion, conversion is not performed accurately. To obtain the accurate conversion result, it is necessary to keep changes in the analog input voltage as small as possible during A/D conversion. One sampling time = 14/fx (1.75 µs, 8 MHzNote) Sampling repeat cycle = 48/fx (6 µs, 8 MHzNote) Note The guaranteed oscillation range of the µPD17134A, 17136A, and 17P136A is 400 kHz to 2.4 MHz. Number of instruction to be executed (Instruction cycle) POKE 123456789 24 GET Read ADCR Sampling Sampling Sampling Set ADCSTRT Previous data Initial value 80H Most significant bit determined High-order 2 bits are determined ADCSTRT ADCEND 8-bit data register All eight bits are vaild. |
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