UPD17P136ACT datasheet(75/292 Pages) NEC

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CHAPTER 7 SYSTEM REGISTER (SYSREG)

Example 3. Clearing data memory of 00H-0FH to 0

M000 MEM

0.00H

MOV

IXL, #0

; IX

← 0

MOV

IXM, #0

;

MOV

IXH, #0

; MPE

← 0

LOOP:

PSW, #.DF.IXE AND 0FH ; IXE

← 1

MOV

M000, #0

; Set data memory specified by IX to 0

INC

; IX

← IX + 1

AND

PSW, #1110B

; IXE

← 0, Remains address 7FH even if modified

; by IX because IXE is address 7FH.

SKE

IXM, #7

; Row address 7 ?

LOOP

; If not 7 then LOOP (row address is not cleared)

4. Processing an array

As shown in Figure 7-14, when an operation

A(N)

← A(N) + 4 (0 ≤ N ≤ 15)

is executed to element A (N) of a one-dimensional array with each element 8 bits long, the following

instructions are executed.

M000 MEM

0.00H

M001 MEM

0.01H

MOV

IXH, #0

MOV

IXM, #N SHR 3

; Sets offset of row address

MOV

IXL, #N SHL 1 AND 0FH

; Sets offset of column address

PSW, #.DF.IXE AND 0FH ; IXE

← 1

ADD

M000, #4

ADDC

M001, #0

; A(N)

← A(N) + 4

In the above example, the value of N shifted 1 bit to the left (i.e., the value of N multiplied by 2) is

set to the index register because one element is 8 bits long.

Figure 7-14. Operation Example When IXE = 1 and MPE = 0 (Array Processing)

0123456789

Column address

System register

A (0)

A (8)

A (1)

A (9)

A (2)

A (10)

A (3)

A (11)

A (4)

A (12)

A (5)

A (13)

A (6)

A (14)

A (7)

A (15)

A (0)

00H

01H

UPD17P136ACT Datasheet(PDF) 75 Page - NEC

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