UPD17P136ACT datasheet(23/292 Pages) NEC

23 / 292 page

CHAPTER 1 GENERAL DESCRIPTION

1.3 BLOCK DIAGRAM

Remarks 1.

The terms CMOS and N-ch in square brackets indicate the output form of the port.

CMOS : CMOS push-pull output

N-ch

: N-channel open-drain output (Each pin can contain pull-up resistor bit-wise as specified

using a mask option.)

The devices in parentheses are effective only in the case of program memory write/verify mode of

the

µPD17P136A and µPD17P137A.

Notes 1.

The ROM (or PROM) capacity of each product is as follows:

1024

× 16 bits :

µPD17134A, 17135A

2048

× 16 bits :

µPD17136A, 17137A, 17P136A, 17P137A

The stack capacity of each product is as follows:

× 10 bits

µPD17134A, 17135A

× 11 bits

µPD17136A, 17137A

POWER-ON/

POWER-DOWN

RESET

VDD

P0A0

P0A1

P0A2

P0A3

ALU

ROM/

One-Time

PROM

Program counter

StackNote2

P0A

(CMOS)

Clock

divider

System clock

generator

XIN

XOUT

/2N

CPU CLOCK CLK STOP

P0B0

P0B1

P0B2

P0B3

P0C0/ADC0

P0C1/ADC1

P0C2/ADC2

P0C3/ADC3

P0D0/SCK

P0D1/SO

P0D2/SI

P0D3/TM0OUT

P1A0

P1A1

P1A2

P1A3

P1B0

RESET

RAM

112

× 4 bits

SYSTEM REG.

P0B

(CMOS)

P0C

(CMOS)

A/D

Con-

verter

P0D

(N-ch)

Serial

Inter-

face

Instruction

decoder

P1A

(N-ch)

P1B

Timer 0

Timer 1

IRQTM0

IRQTM1

IRQBTM

Basic interval timer

Interrupt

controller

IRQTM0

IRQTM1

IRQBTM

IRQSIO

ZEROCROSS

detector

INT

TM0

IRQSIO

GND

fX/2N

(VPP)

(CLK)Note2

Note1

UPD17P136ACT Datasheet(PDF) 23 Page - NEC

UPD17P136ACT Datasheet(HTML) 23 Page - NEC

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